The book is aimed on the development of a cheap and universal image processing camera system (IPCAM), for the possibility of further arbitrary modifications and simple reconfiguration for image processing applications or vision and motion systems. The system should be also powerful enough to be able to obtain and process images from the digital camera sensor in a real time. Further part of the book is design and implementation of the functions for image processing applications and communication with other superior system/s.
Object Tracking using Computer Vision has been a highly discussed topic within the AI and ML community for a while now, but most hardware real-time applications within this realm have long been reliant on having either high-speed dedicated sequential processors for processing the huge amount of calculations necessary or a real-time embedded processor setup which can work faster than traditional sequential processors but still have some of their limitations. Ideally for a real-time application we want our system to have as much parallel signal processing capability as possible. Hence, to leverage the much faster signal processing capability this project adopts a Verilog based HDL implementation on the Zedboard FPGA platform. This project proposes a low-cost design for real-time object tracking implementation on the Zedboard FPGA. The algorithm used to achieve this implementation works in a parallel processing configuration for minimum latency and uses thresholding techniques to detect color and geometric centroid calculations to track positions for objects of interest. The project is extended and implemented on a pan/tilt mechanical module having positional servo motors to control X and Y directional movement that will serve as a mount for the CMOS OV7670 Pmod Camera for complete real time object tracking. This project has potential in computer vision related applications. The hardware design files made using Verilog for this project are implemented using Vivado IDE provided by Xilinx.
This book discusses the design of multi-camera systems and their application to fields such as the virtual reality, gaming, film industry, medicine, automotive industry, drones, etc. The authors cover the basics of image formation, algorithms for stitching a panoramic image from multiple cameras, and multiple real-time hardware system architectures, in order to have panoramic videos. Several specific applications of multi-camera systems are presented, such as depth estimation, high dynamic range imaging, and medical imaging.
This publication addresses distributed embedded smart cameras –cameras that perform on board analysis and collaborate with other cameras. This book provides the material required to better understand the architectural design challenges of embedded smart camera systems, the hardware/software ecosystem, the design approach for and applications of distributed smart cameras together with the state-of-the-art algorithms. The authors concentrate on the architecture, hardware/software design, realization of smart camera networks from applications to architectures, in particular in the embedded and mobile domains.
This book constitutes the refereed proceedings of the 21st International Symposium on VLSI Design and Test, VDAT 2017, held in Roorkee, India, in June/July 2017. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification.
Machine vision camera is becoming more popular in the industry. USB 3.0 interface support 5Gbps transmission, and is a low-cost and fast way to transmit video signals from sensors to computers. However, most image sensors are incompatible with USB 3.0 protocol, and cannot directly connect to USB 3.0. In this report, we present the development of the hardware design of a USB 3.0 multi-purpose camera using the Cypress microprocessor. Our camera also has a FPGA module as an adaptive part to provide protocol translation, voltage level conversion, serial to parallel conversion, multi-channel data collection, and clock synthesis. We also discuss some important principles of system and schematic design, and emphasize a few critical PCB routing rules for assurance of PCB integrity. Some testing outcomes are provided to illustrate the hardware functionality and algorithm running results, which verify the success of the design and the performance of the camera.
The thesis covers detailed description of a development platform for video processing system targeted for ON-camera applications. Platforms such as the Zynq and Xilinx Inc., integrate high-performance processing, programmable digital intellectual property (IP), core peripheral, and input-output video signal interfaces into a single FPGA chip. The advantages of using this method include size, weight, and power (SWAP) requirements in applications such as pilot helmet vision and binocular video processors. The contents include an overview of the processor system and IP cores on the FPGA architecture, video processing IP cores, Integrated Design Environment (IDE) tools, and case studies on grey scale conversion and canny edge detection. The results from the case studies display the effectiveness of the design and implementation methodology. Programmable IP core peripherals enable real-time processing, which is difficult to meet under SWAP constraints using software alone. The thesis presents studies on the design and implementation methodology and FPGA video processor platform.
This volume represents the proceedings of the 2014 3rd International Conference on Innovation, Communication and Engineering (ICICE 2014). This conference was held in Guiyang, Guizhou, P.R. China, October 17-22, 2014. The conference provided a unified communication platform for researchers in a wide range of fields from information technology,
Digital cameras, both in traditional form factors and as parts of cell phones, have become ubiquitous over the last decade. But for the most part, they remain black boxes to the end-user, and cannot be reprogrammed or modified. This has become an obstacle to researchers in the new field of computational photography, who want to use the growing computing power of digital cameras to create images no traditional camera could produce. This dissertation presents the Frankencamera platform, a digital camera system designed for computational photography. The Frankencamera is a fully open, fully programmable digital camera, which can be easily modified to test out new research ideas. The Frankencamera architecture allows for per-frame control of the capture process, and accurate synchronization of all the components that make up the camera. Based on this architecture, this dissertation details two hardware platforms: the F2, a flexible custom-built camera; and the Nokia N900, a commercial smartphone. Both platforms can be easily programmed at a high level using the FCam API, written to embody the Frankencamera architecture. Finally, this dissertation presents several sample applications for the Frankencamera platform. Several of these applications could not have been developed for any existing camera platform, and the ease and speed at which they were written show that the Frankencamera platform is a compelling tool for computational photography.
This dissertation presents a scalable image/video platform with approximate computing design on Field-Programmable Gate Array (FPGA). The platform is able to capture images in real time with a low-cost OV7670 camera and display the original, in-process and final results of images on a VGA-interfaced monitor. To make the platform reusable and expandable, the design with Verilog Hardware Description Language (HDL) and the verification environment including six Open Verification Components (OVCs) are provided. Compared to prior works, our proposed work achieves the least FPGA resource cost (753 Look Up Tables (LUTs) and 277 Registers) on the design of a Camera-FPGA-VGA platform. Furthermore, we present a novel approximate design library with FPGA and provide several slice-energy cost solutions corresponding to different application constrains. Specifically three approximations of multipliers and two approximations of adders, along with the exact designs, are presented and integrated as twelve benchmarks to implement RGB to grayscale conversion as a case study. Experimental results show that the minimum slice-energy cost, integrated with approximate\#2 adder and approximate\#3 multiplier, achieves 25.17% slice-energy saving compared with the exact design by sacrificing the quality of results as 5.69% error for multiplier and 2.85% for adder.
