RF receiver front-end design for the mobile terminals has become a challenging task. The need to share the receiver hardware over multiple RF frequency bands and RF standards; the drive toward reduction in external components and filters; low power consumption targets; deep sub-micron CMOS implementation for SoC applications; and high dynamic range requirements have created an imposing design challenge for the RF receiver front-end. In this research we have taken an objective look at this design challenge and addressed it at various levels.
CMOS Cellular Receiver Front-Ends: from Specification to Realization deals with the design of the receive path of a highly-integrated CMOS cellular transceiver for the GSM-1800 cellular system. The complete design trajectory is covered, starting from the documents describing the standard down to the systematic development of CMOS receiver ICs that comply to the standard. The design of CMOS receivers is tackled at all abstraction levels: from architecture level, via circuit level, down to the device level, and the other way around. The theoretical core of the book discusses the fundamental and more advanced aspects of RF CMOS design. It focuses specifically on all aspects of the design of high-performance CMOS low-noise amplifiers.
Current advances in wireless receiver technologies are primarily driven by the need for cost reduction through (1) integration of a radio, an ADC and a digital processor on a single CMOS die, and (2) the design of low-power multi-standard capable receivers. However, due to the spectrum scarcity, future wireless standards, such as LTE, present a whole new set of challenges for radio system design. For example, LTE's highly fragmented spectrum requires multiple chipsets for support. Due to this cost overhead, there is no global LTE-enabled device available in the market now. Moreover, while carrier aggregation (CA) added to LTE brings unparalleled data rate improvement, it seriously complicates the RF frontend design. Modern commercial LTE solutions include multiple chipsets to support various scenarios of CA, which is not cost effective. This work focuses on novel receiver architectures that address the design challenges associated with LTE-Advance from two perspectives: (1) a receiver that is capable of wide-frequency range of operation to cover all the LTE bands and (2) a single highly linear RF frontend to support non-contiguous-in-band CA. A novel sigma-delta-based direct-RF-to-digital receiver architecture is introduced in this work as an example of a complete integrated RF-to-digital frontend design capable to cover all the LTE bands. The design is implemented in 65 nm CMOS technology and the SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB over the 400 MHz to 4 GHz frequency range. In a different example, we propose a passive-mixer-first receiver system to provide CA support in a cost-effective and power-efficient manner. Mixer-first receiver's superb linearity performance enables the possibility of a single receiver processing the entire LTE RX band, while most of the signal conditioning can be pushed into DSP to enjoy the benefit of process scaling. This design has been demonstrated in a 28 nm bulk CMOS technology, and the overall system achieves 3 dB NF, 15 dBm IIP3 and 35 dB gain with 60 mW of power.
"Fuelled by the ever increasing demand for wireless products and the advent of deep submicron CMOS, RF ICs have become fairly commonplace in the semiconductor market. This has given rise to a new breed of Systems-On-Chip (SOCs) with RF front-ends tightly integrated along with digital, analog and mixed signal circuitry. However, the reliability of the integrated RF front-end continues to be a matter of significant concern and considerable research. A major challenge to the reliability of RF ICs is the fact that their performance is also severely degraded by wide tolerances in on-chip passives and package parasitics, in addition to process related faults. Due to the absence of contact based testing solutions in embedded RF SOCs (because the very act of probing may affect the performance of the RF circuit), coupled with the presence of very few test access nodes, a Built In Self Test approach (BiST) may prove to be the most efficient test scheme. However due to the associated challenges, a comprehensive and low-overhead BiST methodology for on-chip testing of RF ICs has not yet been reported in literature. In the current work, an approach to RF self-test that has hitherto been unexplored both in literature and in the commercial arena is proposed. A sensitive current monitor has been used to extract variations in the supply current drawn by the circuit-under-test (CUT). These variations are then processed in time and frequency domain to develop signatures. The acquired signatures can then be mapped to specific behavioral anomalies and the locations of these anomalies. The CUT is first excited by simple test inputs that can be generated on-chip. The current monitor extracts the corresponding variations in the supply current of the CUT, thereby creating signatures that map to various performance metrics of the circuit. These signatures can then be post-processed by low overhead on-chip circuitry and converted into an accessible form. To be successful in the RF domain any BIST architecture must be minimally invasive, reliable, offer good fault coverage and present low real estate and power overheads. The current-based self-test approach successfully addresses all these concerns. The technique has been applied to RF Low Noise Amplifiers, Mixers and Voltage Controlled Oscillators. The circuitry and post-processing techniques have also been demonstrated in silicon (using the IBM 0.25 micron RF CMOS process). The entire self-test of the RF front-end can be accomplished with a total test time of approximately 30 [microseconds], which is several orders of magnitude better than existing commercial test schemes"--Abstract.
This book discusses a number of challenges faced by designers of wireless receivers, given complications caused by the shrinking of electronic and mobile devices circuitry into ever-smaller sizes and the resulting complications on the manufacturability, production yield, and the end price of the products. The authors describe the impact of process technology on the performance of the end product and equip RF designers with countermeasures to cope with such problems. The mechanisms by which these problems arise are analyzed in detail and novel solutions are provided, including design guidelines for receivers with robustness to process variations and details of circuit blocks that obtain the required performance level. Describes RF receiver frontends and their building blocks from a system- and circuit-level perspective; Provides system-level analysis of a generic RF receiver frontend with robustness to process variations; Includes details of CMOS circuit design at 60GHz and reconfigurable circuits at 60GHz; Covers millimeter-wave circuit design with robustness to process variations.
Nanometer CMOS RFICs for Mobile TV Applications focuses on how to break the trade-off between power consumption and performance (linearity and noise figure) by optimizing the mobile TV front-end dynamic range in three hierarchical levels: the intrinsic MOSFET level, the circuit level, and the architectural level. It begins by discussing the fundamental concepts of MOSFET dynamic range, including nonlinearity and noise. It then moves to the circuit level introducing the challenges associated with designing wide-dynamic range, variable-gain, broadband low-noise amplifiers (LNAs). The book gives a detailed analysis of a new noise-canceling technique that helps CMOS LNAs achieve a sub - 2 dB wideband noise figure. Lastly, the book deals with the front-end dynamic range optimization process from the systems perspective by introducing the active and passive automatic gain control (AGC) mechanism.
The research activity carried out during this PhD consists on the design of radio- frequency integrated circuits, for ultra-wideband (UWB) and millimeter-wave sys- tems, and covers the following topics: (i) radio-frequency integrated circuits for low-power transceivers for wireless local networks; (ii) fully integrated UWB radar for cardio-pulmonary monitoring in 90nm CMOS technology; (iii) 60-GHz low noise amplifer (LNA) in 65nm CMOS technology.
