A transistor-level, design-intensive overview of high speed and high frequency monolithic integrated circuits for wireless and broadband systems from 2 GHz to 200 GHz, this comprehensive text covers high-speed, RF, mm-wave, and optical fibre circuits using nanoscale CMOS, SiGe BiCMOS, and III-V technologies. Step-by-step design methodologies, end-of chapter problems, and practical simulation and design projects are provided, making this an ideal resource for senior undergraduate and graduate courses in circuit design. With an emphasis on device-circuit topology interaction and optimization, it gives circuit designers and students alike an in-depth understanding of device structures and process limitations affecting circuit performance.
This volume of Analog Circuit Design concentrates on three topics: (X)DSL and other communication systems; RF MOST models; and integrated filters and oscillators. The book comprises five chapters on the first topic with six each on the other two, all written by internationally recognized experts. They are tutorial in nature and together make a substantial contribution to improving the design of analog circuits. The book is divided into three parts: Part I: (X)DSL and other Communication Systems presents some examples of recent improved modem techniques which have resulted in much higher transmission speeds over the local telephone network. It also presents components for the implementation of different standards. Part II: RF MOST Models investigates the state of the art in RF MOST models. It compares the existing BSIM3v3, Philips' Model 9 and the EKV model with respect to their capability to accurately predict GHz performance with submicron CMOST technologies. It shows how it has now become quite feasible to model a MOST at very high frequencies, giving rise to an increased use of MOST technologies in RF applications. Part III: Integrated Filters and Oscillators illustrates how the increasing use of communication tools goes hand-in-hand with the design of analog filters and oscillators with greater flexibility and higher bandwidth.
This book constitutes the refereed proceedings of the 17th International Symposium on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers presented were carefully reviewed and selected from 162 submissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VLSI design, testing and verification, embedded systems, emerging technology.
The book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conference on Microelectronics, Electromagnetics and Telecommunication (ICMEET 2018), organised by GVP College of Engineering (A), Andhra Pradesh, India. The respective papers were written by scientists, research scholars and practitioners from leading universities, engineering colleges and R&D institutes from all over the world, and share the latest breakthroughs in and promising solutions to the most important issues facing today’s society.
Inhaltsangabe:Abstract: The Bluetooth wireless technology is the worlds new short-range RF transmission standard for small form factor, low-cost, short-range radio links between portable or desktop devices. The technology promises to eliminate the confusion of cables, connectors and protocols confounding communications between today high tech products. In the first step a 2.45 GHz Low Noise Amplifier (LNA), intended for use in a Bluetooth receiver, has been designed in a standard 0.18 um CMOS process. The amplifier provides a simulated switchable forward voltage gain of +16 / -7.7 dB with a simulated noise Figure (NF) of only 3 dB while drawing 2.8 mA from a 1.8 V supply. The die area of the LNA (pads included) is 0.79 mm2. In the second step a 2.45 GHz Power Amplifier (PA), also intended for the Bluetooth standard, has been designed in the same 0.18 um CMOS process as for the LNA. The class-A PA achieves a simulated forward gain (S21) of 23 dB and a simulated output 1 dB compression point (P1dB ) of 5.5 dBm, with a power-added efficiency (PAE) of 23 % while drawing 15.8 mA from a 1.8 V supply. The die area of the PA (pads included) is 2.1 mm2. Inhaltsverzeichnis:Table of Contents: 1.Introduction1 1.1Motivation1 1.2Organization2 2.The Bluetooth standard3 2.1Bluetooth as branding-name3 2.2Bluetooth RF requirements4 2.3System design4 2.3.1Receiver architectures4 2.3.2Transmitter architectures6 3.RF CMOS technology9 3.1The foundry9 3.1.1Technology overview9 3.1.2Process Characteristic9 3.2Design Flow10 3.2.1Cadence10 3.2.2SpectreRF10 4.Integrated spiral inductors11 4.1View and physical dimension of spiral11 4.2Model for on-chip spiral inductors12 5.Low Noise Amplifier13 5.1Architecture choices13 5.1.1Recent studies13 5.1.2LNA Architectures13 5.1.3Architecture properties14 5.1.4Architecture choice14 5.2A little piece of theory15 5.2.1Standard MOS noise model15 5.2.2Noise Figure16 5.2.3Input impedance16 5.2.4Voltage Gain18 5.2.5Stability19 5.2.6Noise Figure20 5.3Design approach for the LNA21 5.3.1Circuit topology21 5.3.2RF circuit design strategy21 5.3.3DC operating point design strategy23 5.3.4Input matching24 5.3.5Voltage gain25 5.3.6Noise Figure26 5.3.7Stability27 5.3.8LNA core schematics with component values28 5.4Design approach for the attenuation path of the LNA29 5.4.1Circuit Topology29 5.4.2Switching network29 5.4.3Input matching31 5.4.4Attenuation32 5.4.5Switchable LNA schematics with [...]
Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.
MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible. The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O. Contents: Achieving Analog Accuracy in Nanometer CMOS (M P Flynn et al.); Self-Induced Noise in Integrated Circuits (R Gharpurey & S Naraghi); High-Speed Oversampling Analog-to-Digital Converters (A Gharbiya et al.); Designing LC VCOs Using Capacitive Degeneration Techniques (B Jung & R Harjani); Fully Integrated Frequency Synthesizers: A Tutorial (S T Moon et al.); Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits (D J Allstot et al.); Equalizers for High-Speed Serial Links (P K Hanumolu et al.); Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation (C P Yue et al.). Readership: Technologists, scientists, and engineers in the field of high-speed communication circuits. It can also be used as a textbook for graduate and advanced undergraduate courses.
This work covers the design of CMOS fully integrated low power low phase noise voltage controlled oscillators for telecommunication or datacommuni- tion systems. The need for low power is obvious, as mobile wireless telecommunications are battery operated. As wireless telecommunication systems use oscillators in frequency synthesizers for frequency translation, the selectivity and signal to noise ratio of receivers and transmitters depend heavily on the low phase noise performance of the implemented oscillators. Datacommunication s- tems need low jitter, the time-domain equivalent of low phase noise, clocks for data detection and recovery. The power consumption is less critical. The need for multi-band and multi-mode systems pushes the high-integration of telecommunication systems. This is o?ered by sub-micron CMOS feat- ing digital ?exibility. The recent crisis in telecommunication clearly shows that mobile hand-sets became mass-market high-volume consumer products, where low-cost is of prime importance. This need for low-cost products - livens tremendously research towards CMOS alternatives for the bipolar or BiCMOS solutions in use today.
This book provides the most comprehensive and in-depth coverage of the latest circuit design developments in RF CMOS technology. It is a practical and cutting-edge guide, packed with proven circuit techniques and innovative design methodologies for solving challenging problems associated with RF integrated circuits and systems. This invaluable resource features a collection of the finest design practices that may soon drive the system-on-chip revolution. Using this book's state-of-the-art design techniques, one can apply existing technologies in novel ways and to create new circuit designs for the future.
This book shows that with the use of metamaterials, one can have coherent THz signal generation, amplification, transmission, and detection for phase-arrayed CMOS transistors with significantly improved performance. Offering detailed coverage from device to system, the book describes the design and application of metamaterials in actual CMOS integrated circuits, includes real circuit examples and chip demonstrations with measurement results, and also evaluates system performance after CMOS-based system-on-chip integration. The book reflects the latest research progress and provides a state-of-the-art reference on CMOS-based metamaterial devices and mm-wave and THz systems.
