ICPE '17: ACM/SPEC International Conference on Performance Engineering Apr 22, 2017-Apr 26, 2017 L'Aquila, Italy. You can view more information about this proceeding and all of ACM�s other published conference proceedings from the ACM Digital Library: http://www.acm.org/dl.
Software development is replete with risks. Will the finished software run quickly enough? Will the underlying hardware and network infrastructure be sufficient? Will the system scale? You can now get the answers you need, up-front, in time to act. This book introduces Software Performance Engineering (SPE), a proven step-by-step methodology for predicting the development challenges and performance of any object-oriented system -- and for managing development to achieve performance objectives. Performance experts Connie Smith and Lloyd Williams show how to build quantitative models of software before it is built, analyzing performance based on proposed architecture and design. Learn how to elicit performance objectives, gather relevant data, and evaluate performance throughout development and the rest of the software lifecycle. For software engineers, developers, architects, analysts, performance specialists, project managers, and other IT professionals who want to deliver higher-performance object-oriented software systems.
The “HPI Future SOC Lab” is a cooperation of the Hasso Plattner Institute (HPI) and industry partners. Its mission is to enable and promote exchange and interaction between the research community and the industry partners. The HPI Future SOC Lab provides researchers with free of charge access to a complete infrastructure of state of the art hard and software. This infrastructure includes components, which might be too expensive for an ordinary research environment, such as servers with up to 64 cores and 2 TB main memory. The offerings address researchers particularly from but not limited to the areas of computer science and business information systems. Main areas of research include cloud computing, parallelization, and In-Memory technologies. This technical report presents results of research projects executed in 2020. Selected projects have presented their results on April 21st and November 10th 2020 at the Future SOC Lab Day events.
This book constitutes the refereed proceedings of the 18th European Workshop on Computer Performance Engineering, EPEW 2022, held in Santa Pola, Spain, in September 2022. The 14 papers presented in this volume together with one invited talk were carefully reviewed and selected from 14 submissions. The papers presented at the workshop reflect the diversity of modern performance engineering. The sessions covered a wide range of topics including robustness analysis, machine learning, edge and cloud computing, as well as more traditional topics on stochastic modelling, techniques and tools.
The “HPI Future SOC Lab” is a cooperation of the Hasso Plattner Institute (HPI) and industry partners. Its mission is to enable and promote exchange and interaction between the research community and the industry partners. The HPI Future SOC Lab provides researchers with free of charge access to a complete infrastructure of state of the art hard and software. This infrastructure includes components, which might be too expensive for an ordinary research environment, such as servers with up to 64 cores and 2 TB main memory. The offerings address researchers particularly from but not limited to the areas of computer science and business information systems. Main areas of research include cloud computing, parallelization, and In-Memory technologies. This technical report presents results of research projects executed in 2018. Selected projects have presented their results on April 17th and November 14th 2017 at the Future SOC Lab Day events.
This book serves as both a textbook and handbook on the benchmarking of systems and components used as building blocks of modern information and communication technology applications. It provides theoretical and practical foundations as well as an in-depth exploration of modern benchmarks and benchmark development. The book is divided into two parts: foundations and applications. The first part introduces the foundations of benchmarking as a discipline, covering the three fundamental elements of each benchmarking approach: metrics, workloads, and measurement methodology. The second part focuses on different application areas, presenting contributions in specific fields of benchmark development. These contributions address the unique challenges that arise in the conception and development of benchmarks for specific systems or subsystems, and demonstrate how the foundations and concepts in the first part of the book are being used in existing benchmarks. Further, the book presents a number of concrete applications and case studies based on input from leading benchmark developers from consortia such as the Standard Performance Evaluation Corporation (SPEC) and the Transaction Processing Performance Council (TPC). Providing both practical and theoretical foundations, as well as a detailed discussion of modern benchmarks and their development, the book is intended as a handbook for professionals and researchers working in areas related to benchmarking. It offers an up-to-date point of reference for existing work as well as latest results, research challenges, and future research directions. It also can be used as a textbook for graduate and postgraduate students studying any of the many subjects related to benchmarking. While readers are assumed to be familiar with the principles and practices of computer science, as well as software and systems engineering, no specific expertise in any subfield of these disciplines is required.
This volume constitutes the papers of several workshops which were held in conjunction with the 38th International Conference on High Performance Computing, ISC High Performance 2023, held in Hamburg, Germany, during May 21–25, 2023. The 49 revised full papers presented in this book were carefully reviewed and selected from 70 submissions. ISC High Performance 2023 presents the following workshops: 2nd International Workshop on Malleability Techniques Applications in High-Performance Computing (HPCMALL) 18th Workshop on Virtualization in High-Performance Cloud Computing (VHPC 23) HPC I/O in the Data Center (HPC IODC) Workshop on Converged Computing of Cloud, HPC, and Edge (WOCC’23) 7th International Workshop on In Situ Visualization (WOIV’23) Workshop on Monitoring and Operational Data Analytics (MODA23) 2nd Workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms: Scalable Infrastructures First International Workshop on RISC-V for HPC Second Combined Workshop on Interactive and Urgent Supercomputing (CWIUS) HPC on Heterogeneous Hardware (H3)
This book constitutes the refereed proceedings of the 14th EuropeanWorkshop on Computer Performance Engineering, EPEW 2017, held in Berlin,Germany, in September 2017. The 18 papers presented together with the abstracts of two invited talks in this volume were carefully reviewed and selected from 30 submissions. The papers presented at the workshop reflect the diversity of modern performanceengineering, with topics ranging from advances in Markov models; advances in quantitative analysis; model checking; and cyber-physical systems to performance, energy and security.
This book describes how we can design and make efficient processors for high-performance computing, AI, and data science. Although there are many textbooks on the design of processors we do not have a widely accepted definition of the efficiency of a general-purpose computer architecture. Without a definition of the efficiency, it is difficult to make scientific approach to the processor design. In this book, a clear definition of efficiency is given and thus a scientific approach for processor design is made possible. In chapter 2, the history of the development of high-performance processor is overviewed, to discuss what quantity we can use to measure the efficiency of these processors. The proposed quantity is the ratio between the minimum possible energy consumption and the actual energy consumption for a given application using a given semiconductor technology. In chapter 3, whether or not this quantity can be used in practice is discussed, for many real-world applications. In chapter 4, general-purpose processors in the past and present are discussed from this viewpoint. In chapter 5, how we can actually design processors with near-optimal efficiencies is described, and in chapter 6 how we can program such processors. This book gives a new way to look at the field of the design of high-performance processors.