Plasma Etching Processes for CMOS Devices Realization
Plasma Etching Processes for CMOS Devices Realization

Author: Nicolas Posseme

Publisher: Elsevier

Published: 2017-01-25

Total Pages: 138

ISBN-13: 0081011962

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Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent. Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography. This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization. Helps readers discover the master technology used to pattern complex structures involving various materials Explores the capabilities of cold plasmas to generate well controlled etched profiles and high etch selectivities between materials Teaches users how etch compensation helps to create devices that are smaller than 20 nm

Plasma Etching Processes for Interconnect Realization in VLSI
Plasma Etching Processes for Interconnect Realization in VLSI

Author: Nicolas Posseme

Publisher: Elsevier

Published: 2015-04-14

Total Pages: 123

ISBN-13: 0081005903

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This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions.This book focuses on back end of line (BEOL) for high performance device realization and presents an overview of all etch challenges for interconnect realization as well as the current etch solutions proposed in the semiconductor industry. The choice of copper/low-k interconnect architecture is one of the keys for integrated circuit performance, process manufacturability and scalability. Today, implementation of porous low-k material is mandatory in order to minimize signal propagation delay in interconnections. In this context, the traditional plasma process issues (plasma-induced damage, dimension and profile control, selectivity) and new emerging challenges (residue formation, dielectric wiggling) are critical points of research in order to control the reliability and reduce defects in interconnects. These issues and potential solutions are illustrated by the authors through different process architectures available in the semiconductor industry (metallic or organic hard mask strategies). - Presents the difficulties encountered for interconnect realization in very large-scale integrated (VLSI) circuits - Focused on plasma-dielectric surface interaction - Helps you further reduce the dielectric constant for the future technological nodes