As chips continue to scale, power integrity issues are introducing unexpected project complexity and cost. In this book, two leading industry innovators thoroughly discuss the power integrity challenges that engineers face in designing at nanoscale levels, introduce new analysis and management techniques for addressing these issues, and provide breakthrough tools for hands-on problem solving. --
Proven methods for noise-tolerant nanoscale integrated circuit design This leading-edge guide discusses the impact of power integrity from a design perspective, emphasizing phenomena and problems induced by power integrity degradation and the latest design trends, including low-power design. Power Integrity for Nanoscale Integrated Systems describes how these problems can be forecast early in the design process and the countermeasures that can be used to address them, such as the inclusion of inductance and accurate modeling for PI analysis, as well as robust circuit design. Detailed examples and a case study on the IBM POWER7+ processor illustrate real-world applications of the techniques presented in this practical resource. Coverage includes: Significance of power integrity for integrated circuits Supply and substrate noise impact on circuits Clock generation and distribution with power integrity Signal and power integrity design for I/O circuits Power integrity degradation and modeling Lumped, distributed, and 3D modeling for power integrity Chip temperature and PI impact Low-power techniques and PI impact Power integrity case study using the IBM POWER7+ processor chip Carbon nanotube interconnects for power delivery
With the inclusion of the two new hot topics in signal integrity, power integrity and high speed serial links, this book will be the most up to date complete guide to understanding and designing for signal integrity.
This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.
Consistently Design PDNs That Deliver Reliable Performance at the Right Cost Too often, PDN designs work inconsistently, and techniques that work in some scenarios seem to fail inexplicably in others. This book explains why and presents realistic processes for getting PDN designs right in any new product. Drawing on 60+ years of signal and power integrity experience, Larry Smith and Eric Bogatin show how to manage noise and electrical performance, and complement intuition with analysis to balance cost, performance, risk, and schedule. Throughout, they distill the essence of complex real-world problems, quantify core principles via approximation, and apply them to specific examples. For easy usage, dozens of key concepts and observations are highlighted as tips and listed in quick, chapter-ending summaries. Coverage includes • A practical, start-to-finish approach to consistently meeting PDN performance goals • Understanding how signals interact with interconnects • Identifying root causes of common problems, so you can avoid them • Leveraging analysis tools to efficiently explore design space and optimize tradeoffs • Analyzing impedance-related properties of series and parallel RLC circuits • Measuring low impedance for components and entire PDN ecologies • Predicting loop inductance from physical design features • Reducing peak impedances from combinations of capacitors • Understanding power and ground plane properties in the PDN interconnect • Taming signal integrity problems when signals change return planes • Reducing peak impedance created by on-die capacitance and package lead inductance • Controlling transient current waveform interactions with PDN features • Simple spreadsheet-based analysis techniques for quickly creating first-pass designs This guide will be indispensable for all engineers involved in PDN design, including product, board, and chip designers; system, hardware, component, and package engineers; power supply designers, SI and EMI engineers, sales engineers, and their managers.
This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors’ manuals, and program downloads
This leading-edge circuit design resource offers the knowledge needed to quickly pinpoint transmission problems that can compromise circuit design. Discusses both design and debug issues at gigabit per second data rates.
This thorough review of the fundamental principles associated with signal integrity provides engineering principles behind signal integrity effects, and applies this understanding to solving problems.
This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.
Noise Coupling is the root-cause of the majority of Systems on Chip (SoC) product fails. The book discusses a breakthrough substrate coupling analysis flow and modelling toolset, addressing the needs of the design community. The flow provides capability to analyze noise components, propagating through the substrate, the parasitic interconnects and the package. Using this book, the reader can analyze and avoid complex noise coupling that degrades RF and mixed signal design performance, while reducing the need for conservative design practices. With chapters written by leading international experts in the field, novel methodologies are provided to identify noise coupling in silicon. It additionally features case studies that can be found in any modern CMOS SoC product for mobile communications, automotive applications and readout front ends.
