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Published: 1998

Total Pages: 0

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In recent years, power consumption has become a major concern in the electronic industry. Power reduction can be accelerated in the design cycle by fast and accurate power estimation tools. Since the units of lower-levels of design abstraction are transistors or gates, power estimation becomes a slow process at these levels. Therefore designers need to have tools for fast and accurate power estimation at the higher levels of design abstraction such as register transfer level (RTL). A novel RTL power estimation technique called CRAB-RPE will be presented in this thesis. The CRAB power model is built upon four important properties which most of the previous RTL models did not support at the same time. First, the model is based solely on the first and second-order primary input bit-level transition probabilities which provide detailed information about the primary input bit activity dependency of the circuit. Second, the model is based on the power characterization of a microarchitecture library with a complete range of primary input bit transition probabilities without any assumptions about this activity. Third, the pairwise spatial correlations of the primary input nodes are considered by including second-order crossterms of the primary input switching probabilities. Fourth, the first-order temporal correlations of the primary input bits are considered by including 1 to 1 and binary switching transition probabilities. With the proposed model, fast power estimation can be achieved from input bit-level statistics without further simulation. The model was evaluated using the ISCAS combinational circuit benchmarks and other commonly used micro-architectural circuit blocks. Second-order terms were observed to be important for modeling the low bit activity effects on power dissipation. The CRAB power model returned under 5% of the low-level simulator estimates for either biased single, pair PIN statistics or uniform white noise, DBT-like data.