Non-binary LDPC codes can outperform binary LDPC codes using sum-product algorithm with higher computation complexity. Non-binary LDPC codes based on protographs have the advantage of simple hardware architecture. In the first part of this thesis, we will use EXIT chart analysis to compute the thresholds of different protographs over GF(q). Based on threshold computation, some non-binary protograph-based LDPC codes are designed and their frame error rates are compared with binary LDPC codes. For maximum-likelihood decoder, weight enumerator can predict frame error rate of an LDPC code. In the second part of this thesis, we calculate weight enumerators of protograph-based non-binary LDPC code ensembles both for finite length case and asymptotic case. In addition, the trapping set and stopping set enumerators are presented.
We are undergoing a revolution in data. The ever-growing amount of information in our world has created an unprecedented demand for ultra-reliable, affordable, and resource-efficient data storage systems. Error-correcting codes, as a critical component of any memory device, will play a crucial role in the future of data storage. One particular class of error-correcting codes, known as graph-based codes, has drawn significant attention in both academia and in industry. Graph-based codes offer superior performance compared to traditional algebraic codes. Recently, it has been shown that non-binary graph-based codes, which operate over finite fields rather than binary alphabets, outperform their binary counterparts and exhibit outstanding overall performance. For this reason, these codes are particularly suitable for emerging data storage systems. In this dissertation, we present a comprehensive combinatorial analysis of non-binary graph-based codes. We perform both finite-length and asymptotic analyses for these codes, providing a systematic framework to evaluate and optimize various families of non-binary graph-based codes. In the finite-length case, we provide a mathematical characterization of the error floor problem, including a general definition of absorbing sets over non-binary alphabets. We consider several structured low-density parity-check (LDPC) codes, including quasi-cyclic and spatially-coupled codes, as well as unstructured LDPC codes. We offer design guidelines for non-binary LDPC codes with outstanding performance in extremely low error-rate regimes; making them excellent candidates for data storage applications. In the asymptotic case, we provide a novel toolbox for the evaluation of families of non-binary graph-based codes. By utilizing insights from graph theory and combinatorics, we establish enumerators for a general family of graph-based codes which are constructed based on protographs. We provide asymptotic distributions of codewords and trapping sets for the family of protograph-based codes. Furthermore, we present an asymptotic enumeration of binary and non-binary elementary absorbing sets for regular code ensembles. The contributions of this dissertation can potentially impact a broad range of data storage and communication technologies that require excellent performance in high-reliability regimes.
In this thesis we study Low Density Parity Check (LDPC) and LDPC like codes over non-binary fields. We extend the concepts used for non-binary LDPC codes to generalize Product Accumulate (PA) codes to non-binary fields. We present simulation results that show that PA codes over GF(4) performs considerably better than binary PA codes at smaller block lengths and slightly better at large block lengths. We also propose a trellis based decoding algorithm to decode PA codes and show that its complexity is considerably lower than the message-passing algorithm. In the second part of the thesis we study the convergence properties of non-binary PA codes and non-binary LDPC codes. We use EXIT-charts to study the convergence properties of non-binary LDPC codes with different mean column weights and show why certain irregularities are better. Although the convergence threshold predicted by EXIT-charts on non-binary LDPC codes is quite optimistic we can still use EXIT-charts for comparison between non-binary LDPC codes with different mean column weights.
Using easy-to-follow mathematics, this textbook provides comprehensive coverage of block codes and techniques for reliable communications and data storage. It covers major code designs and constructions from geometric, algebraic, and graph-theoretic points of view, decoding algorithms, error control additive white Gaussian noise (AWGN) and erasure, and dataless recovery. It simplifies a highly mathematical subject to a level that can be understood and applied with a minimum background in mathematics, provides step-by-step explanation of all covered topics, both fundamental and advanced, and includes plenty of practical illustrative examples to assist understanding. Numerous homework problems are included to strengthen student comprehension of new and abstract concepts, and a solutions manual is available online for instructors. Modern developments, including polar codes, are also covered. An essential textbook for senior undergraduates and graduates taking introductory coding courses, students taking advanced full-year graduate coding courses, and professionals working on coding for communications and data storage.
The book is a collection of high-quality peer-reviewed research papers presented in Proceedings of International Conference on Artificial Intelligence and Evolutionary Algorithms in Engineering Systems (ICAEES 2014) held at Noorul Islam Centre for Higher Education, Kumaracoil, India. These research papers provide the latest developments in the broad area of use of artificial intelligence and evolutionary algorithms in engineering systems. The book discusses wide variety of industrial, engineering and scientific applications of the emerging techniques. It presents invited papers from the inventors/originators of new applications and advanced technologies.
A family of low-density lattice codes (LDLC) is studied based on Construction-A for lattices. The family of Construction-A codes is already known to contain a large capacity-achieving subset. Parallels are drawn between coset non-binary low-density parity-check (LDPC) codes and nested low-density Construction-A lattices codes. Most of the related research in LDPC domain assumes optimal power allocation to encoded codeword. The source coding problem of mapping message to power optimal codeword for any LDPC code is in general, NP-hard. In this thesis, we present a novel method for encoding and decoding lattice based on non-binary LDPC codes using message-passing algorithms.
Comprehensive introduction to non-binary error-correction coding techniques Non-Binary Error Control Coding for Wireless Communication and Data Storage explores non-binary coding schemes that have been developed to provide an alternative to the Reed – Solomon codes, which are expected to become unsuitable for use in future data storage and communication devices as the demand for higher data rates increases. This book will look at the other significant non-binary coding schemes, including non-binary block and ring trellis-coded modulation (TCM) codes that perform well in fading conditions without any expansion in bandwidth use, and algebraic-geometric codes which are an extension of Reed-Solomon codes but with better parameters. Key Features: Comprehensive and self-contained reference to non-binary error control coding starting from binary codes and progressing up to the latest non-binary codes Explains the design and construction of good non-binary codes with descriptions of efficient non-binary decoding algorithms with applications for wireless communication and high-density data storage Discusses the application to specific cellular and wireless channels, and also magnetic storage channels that model the reading of data from the magnetic disc of a hard drive. Includes detailed worked examples for each coding scheme to supplement the concepts described in this book Focuses on the encoding, decoding and performance of both block and convolutional non-binary codes, and covers the Kötter-Vardy algorithm and Non-binary LDPC codes This book will be an excellent reference for researchers in the wireless communication and data storage communities, as well as development/research engineers in telecoms and storage companies. Postgraduate students in these fields will also find this book of interest.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this thesis, three decoding algorithms and corresponding VLSI architectures are proposed for NB-LDPC codes to lower the computational complexity and memory requirement. The first design is based on the proposed relaxed Min-max decoding algorithm. A novel relaxed check node processing scheme is proposed for the Min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p̂) can be uniquely represented by a linear combination of $p$ independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25̂) can achieve 52% higher efficiency in terms of throughput-over-area ratio. The second design is based on a proposed enhanced iterative hard reliability-based majority-logic decoding. The recently developed iterative hard reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. Novel schemes are proposed for the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E- )IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Many existing NB-LDPC code construction methods lead to quasi-cyclic or cyclic codes. Both types of codes are considered in our design. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous designs based on the Min-max decoding algorithm, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss. The third design is based on a proposed check node decoding scheme using power representation of finite field elements. Novel schemes are proposed for the Min-max check node processing by making use of the cyclical-shift property of the power representation of finite field elements. Compared to previous designs based on the Min-max algorithm with forward-backward scheme, the proposed check node units (CNUs) do not need the complex switching network. Moreover, the multiplications of the parity check matrix entries are efficiently incorporated. For a Min-max NB-LDPC decoder over GF(32), the proposed scheme reduces the CNU area by at least 32%, and leads to higher clock frequency.
