Written from an engineering standpoint, this book provides the theoretical background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOS nanoscale transistors. A wealth of applications, illustrations and examples connect the methods described to all the latest issues in nanoscale MOSFET design. Key areas covered include: • Transport in arbitrary crystal orientations and strain conditions, and new channel and gate stack materials • All the relevant transport regimes, ranging from low field mobility to quasi-ballistic transport, described using a single modeling framework • Predictive capabilities of device models, discussed with systematic comparisons to experimental results
A comprehensive advanced level examination of the transport theory of nanoscale devices Provides advanced level material of electron transport in nanoscale devices from basic principles of quantum mechanics through to advanced theory and various numerical techniques for electron transport Combines several up-to-date theoretical and numerical approaches in a unified manner, such as Wigner-Boltzmann equation, the recent progress of carrier transport research for nanoscale MOS transistors, and quantum correction approximations The authors approach the subject in a logical and systematic way, reflecting their extensive teaching and research backgrounds
To push MOSFETs to their scaling limits and to explore devices that may complement or even replace them at molecular scale, a clear understanding of device physics at nanometer scale is necessary. Nanoscale Transistors provides a description on the recent development of theory, modeling, and simulation of nanotransistors for electrical engineers, physicists, and chemists working on nanoscale devices. Simple physical pictures and semi-analytical models, which were validated by detailed numerical simulations, are provided for both evolutionary and revolutionary nanotransistors. After basic concepts are reviewed, the text summarizes the essentials of traditional semiconductor devices, digital circuits, and systems to supply a baseline against which new devices can be assessed. A nontraditional view of the MOSFET using concepts that are valid at nanoscale is developed and then applied to nanotube FET as an example of how to extend the concepts to revolutionary nanotransistors. This practical guide then explore the limits of devices by discussing conduction in single molecules
Most of the recent texts on compact modeling are limited to a particular class of semiconductor devices and do not provide comprehensive coverage of the field. Having a single comprehensive reference for the compact models of most commonly used semiconductor devices (both active and passive) represents a significant advantage for the reader. Indeed, several kinds of semiconductor devices are routinely encountered in a single IC design or in a single modeling support group. Compact Modeling includes mostly the material that after several years of IC design applications has been found both theoretically sound and practically significant. Assigning the individual chapters to the groups responsible for the definitive work on the subject assures the highest possible degree of expertise on each of the covered models.
As silicon CMOS technology continues to scale down its minimum critical dimension, it becomes increasingly difficult to enhance device switching speed due to fundamental limitations. Innovations in device structure and materials are pursued to accommodate improvement in performance as well as reduction in transistor size. For beyond-22-nm CMOS technology, III-V channel FETs are considered as a compelling candidate for extending the device scaling limit of low-power and high-speed operation, owing to their superb carrier transport properties and recent experimental advancements. In this thesis, device simulation, compact modeling, circuit design, circuit performance assessment and estimation of III-V logic transistors are carried out to study key considerations such as device pitch, parasitics, and the importance of PMOS for circuit-level performance. To effectively connect device characteristics with circuit design, a physics-based compact model for digital logic is constructed. The model encompasses effects such as field-confined and spatially-confined trapezoidal quantum well sub-band energies, gate leakage tunneling current and parasitic capacitance. The developed compact model contains only three fitting parameters and is verified by experiment and circuit simulations. The compact model enables other bodies of work for the purpose of circuit-level design and performance estimation. To demonstrate the capability of the model in a circuit environment we apply the compact model to composite circuits such as FO4 inverter chains and SRAM cache to evaluate and project performance and power trends for beyond-22-nm technology.
This book consists of four chapters to address at different modeling levels for different nanoscale MOS structures (Single- and Multi-Gate MOSFETs). The collection of these chapters in the book are attempted to provide a comprehensive coverage on the different levels of electrostatics and transport modeling for these devices, and relationships between them. In particular, the issue of quantum transport approaches, analytical predictive 2D/3D modeling and design-oriented compact modeling. It should be of interests to researchers working on modeling at any level, to provide them with a clear explanation of theapproaches used and the links with modeling techniques for either higher or lower levels.
The primary aim of this book is to discuss various aspects of nanoscale device design and their applications including transport mechanism, modeling, and circuit applications. . Provides a platform for modeling and analysis of state-of-the-art devices in nanoscale regime, reviews issues related to optimizing the sub-nanometer device performance and addresses simulation aspect and/or fabrication process of devices Also, includes design problems at the end of each chapter
This book provides a comprehensive review of the state-of-the-art in the development of new and innovative materials, and of advanced modeling and characterization methods for nanoscale CMOS devices. Leading global industry bodies including the International Technology Roadmap for Semiconductors (ITRS) have created a forecast of performance improvements that will be delivered in the foreseeable future – in the form of a roadmap that will lead to a substantial enlargement in the number of materials, technologies and device architectures used in CMOS devices. This book addresses the field of materials development, which has been the subject of a major research drive aimed at finding new ways to enhance the performance of semiconductor technologies. It covers three areas that will each have a dramatic impact on the development of future CMOS devices: global and local strained and alternative materials for high speed channels on bulk substrate and insulator; very low access resistance; and various high dielectric constant gate stacks for power scaling. The book also provides information on the most appropriate modeling and simulation methods for electrical properties of advanced MOSFETs, including ballistic transport, gate leakage, atomistic simulation, and compact models for single and multi-gate devices, nanowire and carbon-based FETs. Finally, the book presents an in-depth investigation of the main nanocharacterization techniques that can be used for an accurate determination of transport parameters, interface defects, channel strain as well as RF properties, including capacitance-conductance, improved split C-V, magnetoresistance, charge pumping, low frequency noise, and Raman spectroscopy.
In the summer of 2009, leading professionals from industry, government, and academia gathered for a free-spirited debate on the future trends of microelectronics. This volume represents the summary of their valuable contributions. Providing a cohesive exploration and holistic vision of semiconductor microelectronics, this text answers such questions as: What is the future beyond shrinking silicon devices and the field-effect transistor principle? Are there green pastures beyond the traditional semiconductor technologies? This resource also identifies the direction the field is taking, enabling microelectronics professionals and students to conduct research in an informed, profitable, and forward-looking fashion.
