Design of High Speed Folding and Interpolating Analog-to-digital Converter
Design of High Speed Folding and Interpolating Analog-to-digital Converter

Author: Yunchu Li

Publisher:

Published: 2004

Total Pages:

ISBN-13:

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High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F & I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F & I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F & I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35 ơm CMOS process to verify the ideas. The S/H and F & I ADC prototype is realized in 0.35 [mu]m double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters

Author: Pedro M. Figueiredo

Publisher: Springer Science & Business Media

Published: 2009-03-10

Total Pages: 395

ISBN-13: 1402097166

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Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.

Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter of Embedded Systems
Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter of Embedded Systems

Author: Keh-La Lin

Publisher: Springer Science & Business Media

Published: 2006-01-14

Total Pages: 270

ISBN-13: 0306487268

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One of the main trends of microelectronics is toward design for integrated systems, i.e., system-on-a-chip (SoC) or system-on-silicon (SoS). Due to this development, design techniques for mixed-signal circuits become more important than before. Among other devices, analog-to-digital and digital-to-analog converters are the two bridges between the analog and the digital worlds. Besides, low-power design technique is one of the main issues for embedded systems, especially for hand-held applications. Modular Low-Power, High-Speed CMOS Analog-to-Digital Converter for Embedded Systems aims at design techniques for low-power, high-speed analog-to-digital converter processed by the standard CMOS technology. Additionally this book covers physical integration issues of A/D converter integrated in SoC, i.e., substrate crosstalk and reference voltage network design.

High-speed CMOS Folding and Interpolating Analog-to-digital Converters
High-speed CMOS Folding and Interpolating Analog-to-digital Converters

Author: Michael P. Flynn

Publisher:

Published: 1995

Total Pages: 68

ISBN-13:

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Abstract: "Advances in consumer electronics are creating a demand for high speed, low and medium resolution, analog to digital converters. For reasons of cost and integration the circuitry should be compatible with standard digital CMOS. Low power operation is critical in portable equipment, but also improves product reliability and reduces the cost of packaging. The flash converter is perhaps the simplest conversion architecture, however its area and complexity increase exponentially with resolution, making signal distribution complicated, and power consumption prohibitive. Pipeline techniques are well suited to CMOS but at high sampling rates these converters become complex, and large. Moreover CMOS pipeline converters usually require precision capacitors. Folding and interpolating converters offer the speed of flash type devices but at a fraction of the area and power consumption. Until recently, all published folding and interpolating designs have been implemented in bipolar technology. The performance of bipolar based folding converters has come to rival that of other topologies. In this work we describe a CMOS folding and interpolating architecture. The circuitry can be fabricated with standard digital CMOS processing. A CMOS, folding and interpolating, analog-to-digital conversion architecture is presented. The architecture is fully compatible with standard digital CMOS. For speed the analog circuitry is fully differential, continuous time, current mode and open loop. To insure low noise the digital circuitry is implemented using CMOS current steering logic. A 125Ms/s 8 bit and a 150Ms/s 6 bit prototype are described. Both prototypes were implemented in 1um CMOS. The 8 bit converter occupies approximately 4mm2 and dissipates 250mW from a 5V supply, the 6 bit device is half this size and dissipates 55mW. Both devices can function with a supply voltage of 3.3V."

Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process
Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process

Author: Quincy Kwan-Lun Fung

Publisher:

Published: 2008

Total Pages: 194

ISBN-13: 9780494397350

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This thesis describes the design and implementation of an 8 bit, 2 GSamples/s analog to digital converter for a 0.18 mum SiGe BiCMOS process with a unity gain cut off frequency of 60 GHz. This folding and interpolation ADC consists of a highly linear track-and-hold amplifier (THA) with 10 bit resolution, a differential resistor ladder, four folding amplifiers, an interpolation stage, a comparator array, a digital encoder with bubble error correction scheme and a coarse quantizer. The microchip area is 3.0 x 3.4 mm2 including pads and buffer circuits. Simulation results show that this ADC has a maximum signal-to-noise and distortion ratio (SNDR) of 48.9 dB corresponding to a 7.5 effective number of bits (ENOB) and an effective resolution bandwidth (ERBW) of 700MHz. The circuit demonstrates a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.4 and 0.8 LSB, respectively while consuming 3.1W from a single 3.5 V supply.

An 8-bit, 12.5GS/s Folding-interpolating Analog-to-digital Converter
An 8-bit, 12.5GS/s Folding-interpolating Analog-to-digital Converter

Author: Shohreh Ghetmiri

Publisher:

Published: 2009

Total Pages: 214

ISBN-13: 9780494589304

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The motivation behind this work is to target the demand for high-speed medium-resolution ADCs for satellite communication systems. An 8-bit, 12.5GS/s folding-interpolating ADC was designed in 0.25mum, 190GHz SiGe BiCMOS technology from IHP. The ADC consists of a THA, a reference resistor ladder, folding amplifiers, an interpolating resistor string, a comparator array, a digital encoder, a coarse quantizer and a bit synchronizer.Post-layout simulation results of the ADC verify that its performance meets all the required specifications. By comparison to other high-speed ADCs, implemented in SiGe technologies, the present design features the highest sampling rate for 8-bit resolution ADCs to date with a good FOM (12.9pJ/conversion).The THA and the comparator were implemented experimentally and characterized to verify their performance and to ascertain the possibility of implementing the complete ADC. The experimental results meet the expected specifications and indicate that both circuits are suitable for the implementation of the ADC.

An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter
An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter

Author: Wei An

Publisher:

Published: 2000

Total Pages: 0

ISBN-13:

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This thesis deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional 0.5 [mu]m self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency fT of 25GHz. The high-speed and high-resolution A/D converter has applications in direct IF sampling receivers for wideband communications systems. The folding-interpolating architecture offers an optimum solution for Gsample/s, high-resolution A/D converters in terms of system complexity, power dissipation and chip area. The use of a silicon bipolar process allows the integration of Gsample/s ADCs with DSP systems usually realized by silicon CMOS or BiCMOS processes. The 8-bit, 1-Gsample/s A/D converter consists of a reference ladder; four folding blocks for the fine quantizer and one folding block for the coarse quantizer; interpolation resistive strings; a comparator array; a digital encoder including an EXOR array, an error-correction stage, and a 31-to-5 OR ROM; and a coarse quantizer. All circuit blocks are integrated on one chip. The chip area of the circuitry is 2.5mm x 3.5mm including bonding pads. The converter exhibits a better than 7-bit ENOB with an input signal frequency of 200MHz and at a sampling rate of 1-Gsample/s The maximum power dissipation of the ADC is 2.5W using a 5-V power supply.

High Speed A/D Converters
High Speed A/D Converters

Author: Alfi Moscovici

Publisher: Springer Science & Business Media

Published: 2006-04-18

Total Pages: 239

ISBN-13: 0306469944

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The Analog to Digital Converters represent one half of the link between the world we live in - analog - and the digital world of computers, which can handle the computations required in digital signal processing. These devices are mathematically very complex due to their nonlinear behavior and thus fairly difficult to analyze without the use of simulation tools. High Speed A/D Converters: Understanding Data Converters Through SPICE presents the subject from the practising engineer's point of view rather than from the academic's point of view. A practical approach is emphasized. High Speed A/D Converters: Understanding Data Converters Through SPICE is intended as a learning tool by providing building blocks that can be stacked on top of each other to build higher order systems. The book provides a guide to understanding the various topologies used in A/D converters by suggesting simple methods for the blocks used in an A/D converter. The converters discussed throughout the book constitute a class of devices called undersampled or Nyquist converters. The tools used in deriving the results presented are: TopSpice® by Penzar - a mixed mode SPICE simulator - version 5.90. The files included in Appendix A were written for this tool. However, most circuit files need only minor adjustments to be used on other SPICE simulators such as PSpice, Hspice, IS_Spice and Micro-Cap IV; Mathcad 2000 - Professional by Mathsoft. This tool is very useful in performing FFT analysis as well as drawing some of the graphs. Again, the mathcad files are included to help the user analyze the data. High Speed A/D Converters: Understanding Data Converters Through SPICE not only supplies the models for the A/D converters for SPICE program but also describes the physical reasons for the converter's performance.