Design Modifications and Platform Implementation Procedures for Supporting Dynamic Partial Reconfiguration of FPGA Applications
Design Modifications and Platform Implementation Procedures for Supporting Dynamic Partial Reconfiguration of FPGA Applications

Author:

Publisher:

Published: 2013

Total Pages: 141

ISBN-13:

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Dynamic partial reconfiguration of FPGAs allows systems to autonomously alter sections of their design during runtime based on the state of the system. This functionality provides size, weight, and power benefits that are useful in extreme environments such as space. Therefore, NASA has requested research into the feasibility of using a commercial off-the-shelf software flow to convert a static HDL design to support partial reconfiguration. This project presents an analysis of this conversion process using the Xilinx Partial Reconfiguration Flow to convert the static design for the ITU G.729 Voice Decoder. This paper explores the design modifications that must be made to allow for partial reconfiguration. Furthermore, an in-depth description of how to set up the hardware platform to support the HDL application is provided. Finally, timing and size data are presented and analyzed to empirically show the benefits and limitations of using dynamic partial reconfiguration.

Functional Verification of Dynamically Reconfigurable FPGA-based Systems
Functional Verification of Dynamically Reconfigurable FPGA-based Systems

Author: Lingkan Gong

Publisher: Springer

Published: 2014-10-08

Total Pages: 232

ISBN-13: 3319068385

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This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric. Two implementations of the simulation-only layer are included: Extended Re Channel is a System C library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification.

Partial Reconfiguration on FPGAs
Partial Reconfiguration on FPGAs

Author: Dirk Koch

Publisher: Springer Science & Business Media

Published: 2012-07-25

Total Pages: 306

ISBN-13: 1461412250

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This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

Intelligent Satellite Design and Implementation
Intelligent Satellite Design and Implementation

Author: Jianjun Zhang

Publisher: John Wiley & Sons

Published: 2023-10-13

Total Pages: 228

ISBN-13: 1394198973

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INTELLIGENT SATELLITE DESIGN AND IMPLEMENTATION Integrate cutting-edge technology into spacecraft design with this groundbreaking work Artificial intelligence and machine learning have revolutionized virtually every area of computing and complex engineering, and the design of satellite spacecraft is no exception. Intelligent satellites are increasingly capable of human-like perception, decision-making, and operations, and their problem-solving capacities are still expanding. As AI and machine learning continue to advance, their integration into satellite manufacture will only deepen. Intelligent Satellite Design and Implementation seeks to understand the foundations of this integration and its likely directions in the coming years. Beginning from the basic principles of interaction between artificial intelligence and satellite design and mission planning, the book analyzes a series of current or potential areas of technological advancement to create a comprehensive overview of the subject. Intelligent Satellite Design and Implementation readers will also find: Background information on the introduction and development of artificial intelligence Detailed discussion of topics including autonomous satellite operation, remote sensing satellites, and many more Over 100 illustrations and tables to reinforce key concepts Intelligent Satellite Design and Implementation is ideal for graduate students and advanced undergraduates in engineering, computing, and spacecraft design programs, as well as researchers in these and related fields.

A Novel Partial Reconfiguration Methodology for FPGAs of Multichip Systems
A Novel Partial Reconfiguration Methodology for FPGAs of Multichip Systems

Author: Juan Manuel Galindo

Publisher:

Published: 2008

Total Pages: 108

ISBN-13:

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"A number of SRAM-based field programmable gate arrays (FPGAs) allow for partial reconfiguration (PR). Partial reconfiguration can be used to maximize the resource utilization in these FPGAs. Any large design usually consists of many modular features that are never used all concurrently. An FPGA does not need to implement all these features at the same time provided that it can be reconfigured in a reasonable amount of time to implement the features that can be used simultaneously. The use of partial reconfiguration is ideal in this case, since it allows for just the features that are no longer needed to be replaced by the newly required features. Current methodologies use both external and self partial reconfiguration for this purpose. On mature multichip (MC) systems that have not made use of the PR features of their SRAM-based FPGA(s), however, these methodologies would require changes in the existing FPGA configuration protocol and/or associated hardware outside the array. This thesis presents a novel methodology that makes PR features available to these systems for the purpose of maximizing their FPGA resources without the modifications required by the current methodologies. The proposed methodology reuses an existing data interface to send the PR data to the array and directs this data to the FPGA's internal configuration port. A prototype of this methodology is demonstrated on a commercial color space conversion (CSC) engine design using two Xilinx Virtex-II Pro FPGAs. In addition, the effectiveness of the proposed methodology is quantified by comparing the FPGA resource utilization of the original CSC engine design and that of the partial reconfigurable prototype above. Finally, since the application of partial reconfiguration inherently adds latency to the output of any design, the effects of the proposed methodology on the performance of the CSC engine are also studied and reported. This information will show that reconfiguring and loading the prototyped CSC engine in addition to processing a full image in it takes 683ms, which is within the target of one second."--Abstract.

Reconfigurable System Design and Verification
Reconfigurable System Design and Verification

Author: Pao-Ann Hsiung

Publisher: CRC Press

Published: 2018-10-08

Total Pages: 217

ISBN-13: 1351834924

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Reconfigurable systems have pervaded nearly all fields of computation and will continue to do so for the foreseeable future. Reconfigurable System Design and Verification provides a compendium of design and verification techniques for reconfigurable systems, allowing you to quickly search for a technique and determine if it is appropriate to the task at hand. It bridges the gap between the need for reconfigurable computing education and the burgeoning development of numerous different techniques in the design and verification of reconfigurable systems in various application domains. The text explains topics in such a way that they can be immediately grasped and put into practice. It starts with an overview of reconfigurable computing architectures and platforms and demonstrates how to develop reconfigurable systems. This sets up the discussion of the hardware, software, and system techniques that form the core of the text. The authors classify design and verification techniques into primary and secondary categories, allowing the appropriate ones to be easily located and compared. The techniques discussed range from system modeling and system-level design to co-simulation and formal verification. Case studies illustrating real-world applications, detailed explanations of complex algorithms, and self-explaining illustrations add depth to the presentation. Comprehensively covering all techniques related to the hardware-software design and verification of reconfigurable systems, this book provides a single source for information that otherwise would have been dispersed among the literature, making it very difficult to search, compare, and select the technique most suitable. The authors do it all for you, making it easy to find the techniques that fit your system requirements, without having to surf the net or digital libraries to find the candidate techniques and compare them yourself.

Dynamic Partial Self-Reconfiguration
Dynamic Partial Self-Reconfiguration

Author: Andreas Schallenberg

Publisher: Sudwestdeutscher Verlag Fur Hochschulschriften AG

Published: 2010

Total Pages: 0

ISBN-13: 9783838122632

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This book presents an approach (called OSSS+R) that eases the design of dynamic partial reconfigurable systems based on off-the-shelf FPGAs. An object oriented system description library is extended to allow modeling of such adaptive systems. Reconfigurable hardware is described by means of polymorphism and the concept of virtual hardware. The focus is on quick modeling and flexibility rather than in maximizing the grades of freedom for the design. The models can be simulated to perform functional validation by using a simulation library that is based on SystemC and C/C++. OSSS+R can be automatically synthesized to a RTL model. For demonstration purposes, parts of the transformation are implemented in a tool called Fossy. The generated models are cycle accurate with the original OSSS+R model. The feasibility of the proposed approach is demonstrated by implementing a design as a C++ model and then performing all proposed steps. Finally, the model was implemented on a FPGA prototyping platform.

Optimizing Dynamic Logic Realizations for Partial Reconfiguration of Field Programmable Gate Arrays
Optimizing Dynamic Logic Realizations for Partial Reconfiguration of Field Programmable Gate Arrays

Author: Matthew G. Parris

Publisher:

Published: 2008

Total Pages: 108

ISBN-13:

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Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.