Closing the Gap Between ASIC & Custom

Closing the Gap Between ASIC & Custom

Author: David Chinnery

Publisher: Springer Science & Business Media

Published: 2007-05-08

Total Pages: 422

ISBN-13: 0306478234

DOWNLOAD EBOOK

by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy’s comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.


Closing the Power Gap between ASIC & Custom

Closing the Power Gap between ASIC & Custom

Author: David Chinnery

Publisher: Springer Science & Business Media

Published: 2008-01-23

Total Pages: 392

ISBN-13: 0387689532

DOWNLOAD EBOOK

Explains how to use low power design in an automated design flow, and examine the design time and performance trade-offs Includes the latest tools and techniques for low power design applied in an ASIC design flow Focuses on low power in an automated design methodology, a much neglected area


Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Author: Nadine Azemard

Publisher: Springer

Published: 2007-08-21

Total Pages: 596

ISBN-13: 3540744428

DOWNLOAD EBOOK

This volume features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation. Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.


Reuse Methodology Manual for System-on-a-Chip Designs

Reuse Methodology Manual for System-on-a-Chip Designs

Author: Pierre Bricaud

Publisher: Springer Science & Business Media

Published: 2007-05-08

Total Pages: 306

ISBN-13: 0306476401

DOWNLOAD EBOOK

This revised and updated third edition outlines a set of best practices for creating reusable designs for use in an System-on-a-Chip (SoC) design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world.


Nano-CMOS Design for Manufacturability

Nano-CMOS Design for Manufacturability

Author: Ban P. Wong

Publisher: John Wiley & Sons

Published: 2008-12-29

Total Pages: 408

ISBN-13: 0470382813

DOWNLOAD EBOOK

Discover innovative tools that pave the way from circuit and physical design to fabrication processing Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, including the use of a functional first silicon to support a predictable product ramp. Moreover, they introduce several emerging concepts, including stress proximity effects, contour-based extraction, and design process interactions. This book is the sequel to Nano-CMOS Circuit and Physical Design, taking design to technology nodes beyond 65nm geometries. It is divided into three parts: Part One, Newly Exacerbated Effects, introduces the newly exacerbated effects that require designers' attention, beginning with a discussion of the lithography aspects of DFM, followed by the impact of layout on transistor performance Part Two, Design Solutions, examines how to mitigate the impact of process effects, discussing the methodology needed to make sub-wavelength patterning technology work in manufacturing, as well as design solutions to deal with signal, power integrity, WELL, stress proximity effects, and process variability Part Three, The Road to DFM, describes new tools needed to support DFM efforts, including an auto-correction tool capable of fixing the layout of cells with multiple optimization goals, followed by a look ahead into the future of DFM Throughout the book, real-world examples simplify complex concepts, helping readers see how they can successfully handle projects on Nano-CMOS nodes. It provides a bridge that allows engineers to go from physical and circuit design to fabrication processing and, in short, make designs that are not only functional, but that also meet power and performance goals within the design schedule.


Energy-Efficient Communication Processors

Energy-Efficient Communication Processors

Author: Robert Fasthuber

Publisher: Springer Science & Business Media

Published: 2013-05-29

Total Pages: 306

ISBN-13: 1461449928

DOWNLOAD EBOOK

This book describes a new design approach for energy-efficient, Domain-Specific Instruction set Processor (DSIP) architectures for the wireless baseband domain. The innovative techniques presented enable co-design of algorithms, architectures and technology, for efficient implementation of the most advanced technologies. To demonstrate the feasibility of the author’s design approach, case studies are included for crucial functionality of advanced wireless systems with increased computational performance, flexibility and reusability. Designers using this approach will benefit from reduced development/product costs and greater scalability to future process technology nodes.


Low Power Design Essentials

Low Power Design Essentials

Author: Jan Rabaey

Publisher: Springer Science & Business Media

Published: 2009-04-21

Total Pages: 371

ISBN-13: 0387717137

DOWNLOAD EBOOK

This book contains all the topics of importance to the low power designer. It first lays the foundation and then goes on to detail the design process. The book also discusses such special topics as power management and modal design, ultra low power, and low power design methodology and flows. In addition, coverage includes projections of the future and case studies.


Computing Statistics under Interval and Fuzzy Uncertainty

Computing Statistics under Interval and Fuzzy Uncertainty

Author: Hung T. Nguyen

Publisher: Springer

Published: 2011-11-17

Total Pages: 412

ISBN-13: 3642249051

DOWNLOAD EBOOK

In many practical situations, we are interested in statistics characterizing a population of objects: e.g. in the mean height of people from a certain area. Most algorithms for estimating such statistics assume that the sample values are exact. In practice, sample values come from measurements, and measurements are never absolutely accurate. Sometimes, we know the exact probability distribution of the measurement inaccuracy, but often, we only know the upper bound on this inaccuracy. In this case, we have interval uncertainty: e.g. if the measured value is 1.0, and inaccuracy is bounded by 0.1, then the actual (unknown) value of the quantity can be anywhere between 1.0 - 0.1 = 0.9 and 1.0 + 0.1 = 1.1. In other cases, the values are expert estimates, and we only have fuzzy information about the estimation inaccuracy. This book shows how to compute statistics under such interval and fuzzy uncertainty. The resulting methods are applied to computer science (optimal scheduling of different processors), to information technology (maintaining privacy), to computer engineering (design of computer chips), and to data processing in geosciences, radar imaging, and structural mechanics.


FPGA Architecture

FPGA Architecture

Author: Ian Kuon

Publisher: Now Publishers Inc

Published: 2008

Total Pages: 134

ISBN-13: 1601981260

DOWNLOAD EBOOK

Reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. It is an invaluable reference for engineers and computer scientists.


Processor Design

Processor Design

Author: Jari Nurmi

Publisher: Springer Science & Business Media

Published: 2007-07-26

Total Pages: 534

ISBN-13: 1402055307

DOWNLOAD EBOOK

Here is an extremely useful book that provides insight into a number of different flavors of processor architectures and their design, software tool generation, implementation, and verification. After a brief introduction to processor architectures and how processor designers have sometimes failed to deliver what was expected, the authors introduce a generic flow for embedded on-chip processor design and start to explore the vast design space of on-chip processing. The authors cover a number of different types of processor core.