This book constitutes the refereed proceedings of the 20th International Symposium on Stabilization, Safety, and Security of Distributed Systems, SSS 2018, held in Tokyo, Japan, in November 2018. The 24 revised full papers presented were carefully reviewed and selected from 55 submissions. The papers are organized into three tracks reflecting major trends related to distributed systems: theoretical and practical aspects of stabilizing systems; distributed networks and concurrency; and safety in malicious environments.
The International Conference on Compiler Construction provides a forum for presentation and discussion of recent developments in the area of compiler construction, language implementation and language design. Its scope ranges from compilation methods and tools to implementation techniques for specific requirements on languages and target architectures. It also includes language design and programming environment issues which are related to language translation. There is an emphasis on practical and efficient techniques. This volume contains the papers selected for presentation at CC '94, the fifth International Conference on Compiler Construction, held in Edinburgh, U.K., in April 1994.
This volume coherently present 24 thoroughly revised full papers accepted for the ECAI-94 Workshop on Agent Theories, Architectures, and Languages. There is currently considerable interest, from both the AI and the mainstream CS communities, in conceptualizing and building complex computer systems as collections of intelligent agents. This book is devoted to theoretical and practical aspects of architectural and language-related design and implementation issues of software agents. Particularly interesting is the comprehensive survey by the volume editors, which outlines the key issues and indicates, via a comprehensive bibliography, topics for further reading. In addition, a glossary of key terms in this emerging field and a comprehensive subject index is included.
With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered). This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.
This book gathers high-quality papers presented at the First International Conference on Sustainable Technologies for Computational Intelligence (ICTSCI 2019), which was organized by Sri Balaji College of Engineering and Technology, Jaipur, Rajasthan, India, on March 29–30, 2019. It covers emerging topics in computational intelligence and effective strategies for its implementation in engineering applications.
What does a probabilistic program actually compute? How can one formally reason about such probabilistic programs? This valuable guide covers such elementary questions and more. It provides a state-of-the-art overview of the theoretical underpinnings of modern probabilistic programming and their applications in machine learning, security, and other domains, at a level suitable for graduate students and non-experts in the field. In addition, the book treats the connection between probabilistic programs and mathematical logic, security (what is the probability that software leaks confidential information?), and presents three programming languages for different applications: Excel tables, program testing, and approximate computing. This title is also available as Open Access on Cambridge Core.
This book constitutes the refereed proceedings of the 4th International Symposium on High Performance Computing, ISHPC 2002, held in Kansai Science City, Japan, in May 2002 together with the two workshops WOMPEI 2002 and HPF/HiWEP 2002. The 51 revised papers presented were carefully reviewed and selected for inclusion in the proceedings. The book is organized in topical sections on networks, architectures, HPC systems, Earth Simulator, OpenMP-WOMPEI 2002, and HPF-HiWEP 2002.
Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.
