Discrete wavelet transforms (DWTs) have led the revolutions in image and video coding systems over the past decade. In this book, the DWT is presented from the VLSI design perspective, and the related theories, algorithms, and architectures are discussed for 1D, 2D, and 3D DWT.The book provides a comprehensive analysis and discussion of DWTs and their applications including important materials and the newest developments in wavelet processing. For example, the architecture designs of 2D DWT in JPEG 2000 and the development of motion-compensated temporal filtering (MCTF) are explored./a
Discrete wavelet transforms (DWTs) have led the revolutions in image and video coding systems over the past decade. In this book, the DWT is presented from the VLSI design perspective, and the related theories, algorithms, and architectures are discussed for 1D, 2D, and 3D DWT.The book provides a comprehensive analysis and discussion of DWTs and their applications including important materials and the newest developments in wavelet processing. For example, the architecture designs of 2D DWT in JPEG 2000 and the development of motion-compensated temporal filtering (MCTF) are explored.
The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 1970’s when thousands of transistors were integrated into one single chip. Nowadays we are able to integrate more than a billion transistors on a single chip. However, the term “VLSI” is still being used, though there was some effort to coin a new term ULSI (Ultra-Large Scale Integration) for fine distinctions many years ago. VLSI technology has brought tremendous benefits to our everyday life since its occurrence. VLSI circuits are used everywhere, real applications include microprocessors in a personal computer or workstation, chips in a graphic card, digital camera or camcorder, chips in a cell phone or a portable computing device, and embedded processors in an automobile, et al. VLSI covers many phases of design and fabrication of integrated circuits. For a commercial chip design, it involves system definition, VLSI architecture design and optimization, RTL (register transfer language) coding, (pre- and post-synthesis) simulation and verification, synthesis, place and route, timing analyses and timing closure, and multi-step semiconductor device fabrication including wafer processing, die preparation, IC packaging and testing, et al. As the process technology scales down, hundreds or even thousands of millions of transistors are integrated into one single chip. Hence, more and more complicated systems can be integrated into a single chip, the so-called System-on-chip (SoC), which brings to VLSI engineers ever increasingly challenges to master techniques in various phases of VLSI design. For modern SoC design, practical applications are usually speed hungry. For instance, Ethernet standard has evolved from 10Mbps to 10Gbps. Now the specification for 100Mbps Ethernet is on the way. On the other hand, with the popularity of wireless and portable computing devices, low power consumption has become extremely critical. To meet these contradicting requirements, VLSI designers have to perform optimizations at all levels of design. This book is intended to cover a wide range of VLSI design topics. The book can be roughly partitioned into four parts. Part I is mainly focused on algorithmic level and architectural level VLSI design and optimization for image and video signal processing systems. Part II addresses VLSI design optimizations for cryptography and error correction coding. Part III discusses general SoC design techniques as well as other application-specific VLSI design optimizations. The last part will cover generic nano-scale circuit-level design techniques.
In this thesis, we present a new simple and efficient VLSI architecture (DWT-SA) for computing the Discrete Wavelet Transform. The proposed architecture is systolic in nature, modular and extendible to 1-D or 2-D DWT transform of any size. The DWT-SA has been designed, simulated and implemented in silicon. The following are the features of the DWT-SA architecture: (1) It has an efficient (close to 100%) hardware utilization. (2) It works with data streams of arbitrary size. (3) The design is cascadable, for computation of one, two or three dimensional DWT. (4) It requires a minimum interface circuitry on the chip for purposes of interconnecting to a standard communication bus. The DWT-SA design has been implemented using CMOS 1.2 um technology.
