The symposium provided a forum for reviewing and discussing all aspects of process integration, with special focus on nanoscaled technologies, 65 nm and beyond on DRAM, SRAM, flash memory, high density logic-low power, RF, mixed analog-digital, process integration yield, CMP chemistries, low-k processes, gate stacks, metal gates, rapid thermal processing, silicides, copper interconnects, carbon nanotubes, novel materials, high mobility substrates (SOI, sSi, SiGe, GeOI), strain engineering, and hybrid integration.
Finding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance. Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses: Interconnect functions, characterisations, electrical properties and wiring requirements Low-k materials: fundamentals, advances and mechanical properties Conductive layers and barriers Integration and reliability including mechanical reliability, electromigration and electrical breakdown New approaches including 3D, optical, wireless interchip, and carbon-based interconnects Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.
Advanced semiconductor technology is depending on innovation and less on "classical" scaling. SiGe, Ge, and Related Compounds has become a key component in the arsenal in improving semiconductor performance. This symposium discusses the technology to form these materials, process them, FET devices incorporating them, Surfaces and Interfaces, Optoelectronic devices, and HBT devices.
More than 1,100 TEM images illustrate the science of ULSI The natural outgrowth of VLSI (Very Large Scale Integration), Ultra Large Scale Integration (ULSI) refers to semiconductor chips with more than 10 million devices per chip. Written by three renowned pioneers in their field, ULSI Semiconductor Technology Atlas uses examples and TEM (Transmission Electron Microscopy) micrographs to explain and illustrate ULSI process technologies and their associated problems. The first book available on the subject to be illustrated using TEM images, ULSI Semiconductor Technology Atlas is logically divided into four parts: * Part I includes basic introductions to the ULSI process, device construction analysis, and TEM sample preparation * Part II focuses on key ULSI modules--ion implantation and defects, dielectrics and isolation structures, silicides/salicides, and metallization * Part III examines integrated devices, including complete planar DRAM, stacked cell DRAM, and trench cell DRAM, as well as SRAM as examples for process integration and development * Part IV emphasizes special applications, including TEM in advanced failure analysis, TEM in advanced packaging development and UBM (Under Bump Metallization) studies, and high-resolution TEM in microelectronics This innovative guide also provides engineers and managers in the microelectronics industry, as well as graduate students, with: * More than 1,100 TEM images to illustrate the science of ULSI * A historical introduction to the technology as well as coverage of the evolution of basic ULSI process problems and issues * Discussion of TEM in other advanced microelectronics devices and materials, such as flash memories, SOI, SiGe devices, MEMS, and CD-ROMs
