Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed—combined with extensive experimental validation—collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern. The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots. Defines new complex, sustainable network-on-chip architectures to reduce network latency and energy Develops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniques Describes joint strategies for network- and core-level sustainability Discusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures
The dissertation focuses on power and thermal management strategies to enhance NoC sustainability. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Thus, addressing thermal concerns at different design stages is critical to the success of future generation systems.
This brief focuses on network planning and resource allocation by jointly considering cost and energy sustainability in wireless networks with sustainable energy. The characteristics of green energy and investigating existing energy-efficient green approaches for wireless networks with sustainable energy is covered in the first part of this brief. The book then addresses the random availability and capacity of the energy supply. The authors explore how to maximize the energy sustainability of the network and minimize the failure probability that the mesh access points (APs) could deplete their energy and put the network out of service due to the unreliable energy supply. This brief also studies network resource management issues in green wireless networks to minimize cost. It jointly considers the relay node (RN) placement and sub-carrier allocation (RNP-SA) issues in wireless networks with sustainable energy, and then formulates the problem into a mixed integer non-linear programming problem. Concise and informative, this brief is a useful resource for professionals or researchers studying wireless networks, communication networks, and energy efficiency. Advanced-level students interested in energy technology or communications engineering will also find the material valuable.
[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel’s very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.
The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern massive multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multi-hop metal/dielectric based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon Nanotube (CNT) or millimeter (mm)-wave metal antennas are shown to outperform traditional wire based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies can be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This thesis advocates adoption of such complex network based architectures to design wireless NoCs. This thesis presents a detailed performance analysis of small-world network enabled wireless NoC architectures in terms of achievable bandwidth, energy dissipation, thermal profiles and fault tolerance. The wireless NoC outperforms traditional wireline mesh architecture in terms of all the above-mentioned performance metrics. It also minimizes the effect of wireless link failures on the performance of the NoC. Through cycle accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of a high degree of link failures.
Network-on-Chip (NoC) architectures have emerged as a promising technology for modern computer systems to address the design challenges of high-performance computing systems. Wireless NoC (WNoC) architectures are introduced to improve performance by reducing the core-to-core communication latency. Conventional WNoCs broadcast messages that increase bandwidth-traffic, communication latency, and power consumption. Studies show that directory-based schemes have potential to reduce bandwidth-traffic and improve performance. This work introduces a WNoC architecture with centralized directory (WNoC-CD) and a WNoC architecture with distributed directories (WNoC-DDs) to enhance faster execution by reducing bandwidth-traffic and communication latency. The impacts of uniform and non-uniform distribution of cores into subnets on performance are also studied. VisualSim software package is used to model and simulate a traditional mesh and the proposed WNoC-CD and WNoC-DDs architectures by processing different communication scenarios. Experimental results show that the proposed WNoC-DDs reduces communication latency up to 20.54% and 5.40%, respectively, when compared to mesh and WNoC-CD. Similarly, the proposed WNoC-DDs reduces power consumption up to 73.56% and 19.97%, respectively, when compared to mesh and WNoC-CD. In a WNoC-DDs, each subnet works independently and resolves communication issues simultaneously. Experimental results also show that the non-uniform subnets help reduce communication latency up to 11.11% and reduces power consumption up to 14.76% when compared with the uniform subnets. Non-uniform partitioning provides flexibility of allocating tasks to different sized subnets as needed and thus improves the core utilization to a greater extent.
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. On-Chip Communication Architecures is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends Detailed analysis of all popular standards for on-chip communication architectures Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts Future trends that with have a significant impact on research and design of communication architectures over the next several years
Although the information and communication technology (ICT) industry accounted for only 2 percent of global greenhouse gas emissions in 2007, the explosive increase in data traffic brought about by a rapidly growing user base of more than a billion wireless subscribers is expected to nearly double that number by 2020. It is clear that now is the time to rethink how we design and build our networks. Green Networking and Communications: ICT for Sustainability brings together leading academic and industrial researchers from around the world to discuss emerging developments in energy-efficient networking and communications. It covers the spectrum of research subjects, including methodologies and architectures for energy efficiency, energy-efficient protocols and networks, energy management, smart grid communications, and communication technologies for green solutions. Examines foraging-inspired radio-communication energy management for green multi-radio networks Considers a cross-layer approach to the design of energy-efficient wireless access networks Investigates the interplay between cooperative device-to-device communications and green LTE cellular networks Considers smart grid energy procurement for green LTE cellular networks Details smart grid networking protocols and standards Considering the spectrum of energy-efficient network components and approaches for reducing power consumption, the book is organized into three sections: Energy Efficiency and Management in Wireless Networks, Cellular Networks, and Smart Grids. It addresses many open research challenges regarding energy efficiency for IT and for wireless sensor networks, including mobile and wireless access networks, broadband access networks, home networks, vehicular networks, intelligent future wireless networks, and smart grids. It also examines emerging standards for energy-efficient protocols. Since ICT technologies touch on nearly all sectors of the economy, the concepts presented in this text offer you the opportunity to make a substantial contribution to the reduction of global greenhouse gas emissions.
Recent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.
"Previously, research and design of Network-on-Chip (NoC) paradigms where mainly focused on improving the performance of the interconnection networks. With emerging wide range of low-power applications and energy constrained high-performance applications, it is highly desirable to have NoCs that are highly energy efficient without incurring performance penalty. In the design of high-performance massive multi-core chips, power and heat have become dominant constrains. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance and increase cooling costs. It was proven that Small-world Wireless Network-on-Chip (SWNoC) architecture which replaces multi-hop wire-line path in a NoC by high-bandwidth single hop long range wireless links, reduces the overall energy dissipation when compared to wire-line mesh-based NoC architecture. However, the overall energy dissipation of the wireless NoC is still dominated by wire-line links and switches (buffers). Dynamic Voltage Scaling is an efficient technique for significant power savings in microprocessors. It has been proposed and deployed in modern microprocessors by exploiting the variance in processor utilization. On a Network-on-Chip paradigm, it is more likely that the wire-line links and buffers are not always fully utilized even for different applications. Hence, by exploiting these characteristics of the links and buffers over different traffic, DVFS technique can be incorporated on these switches and wire-line links for huge power savings. In this thesis, a history based DVFS mechanism is proposed. This mechanism uses the past utilization of the wire-line links & buffers to predict the future traffic and accordingly tune the voltage and frequency for the links and buffers dynamically for each time window. This mechanism dynamically minimizes the power consumption while substantially maintaining a high performance over the system. Performance analysis on these DVFS enabled Wireless NoC shows that, the overall energy dissipation is improved by around 40% when compared Small-world Wireless NoCs."--Abstract.
