Advanced Data Converters
Advanced Data Converters

Author: Gabriele Manganaro

Publisher: Cambridge University Press

Published: 2011-11-17

Total Pages: 251

ISBN-13: 1139504746

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Need to get up to speed quickly on the latest advances in high performance data converters? Want help choosing the best architecture for your application? With everything you need to know about the key new converter architectures, this guide is for you. It presents basic principles, circuit and system design techniques and associated trade-offs, doing away with lengthy mathematical proofs and providing intuitive descriptions upfront. Everything from time-to-digital converters to comparator-based/zero-crossing ADCs is covered and each topic is introduced with a short summary of the essential basics. Practical examples describing actual chips, along with extensive comparison between architectural or circuit options, ease architecture selection and help you cut design time and engineering risk. Trade-offs, advantages and disadvantages of each option are put into perspective with a discussion of future trends, showing where this field is heading, what is driving it and what the most important unanswered questions are.

Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems
Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems

Author: Yu Lin

Publisher: Springer

Published: 2015-05-07

Total Pages: 124

ISBN-13: 3319176803

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This book addresses the challenges of designing high performance analog-to-digital converters (ADCs) based on the “smart data converters” concept, which implies context awareness, on-chip intelligence and adaptation. Readers will learn to exploit various information either a-priori or a-posteriori (obtained from devices, signals, applications or the ambient situations, etc.) for circuit and architecture optimization during the design phase or adaptation during operation, to enhance data converters performance, flexibility, robustness and power-efficiency. The authors focus on exploiting the a-priori knowledge of the system/application to develop enhancement techniques for ADCs, with particular emphasis on improving the power efficiency of high-speed and high-resolution ADCs for broadband multi-carrier systems.

Digitally-Assisted Analog and Analog-Assisted Digital IC Design
Digitally-Assisted Analog and Analog-Assisted Digital IC Design

Author: Xicheng Jiang

Publisher: Cambridge University Press

Published: 2015-07-23

Total Pages: 417

ISBN-13: 1316368742

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Achieve enhanced performance with this guide to cutting-edge techniques for digitally-assisted analog and analog-assisted digital integrated circuit design. • Discover how architecture and circuit innovations can deliver improved performance in terms of speed, density, power, and cost • Learn about practical design considerations for high-performance scaled CMOS processes, FinFet devices and architectures, and the implications of FD SOI technology • Get up to speed with established circuit techniques that take advantage of scaled CMOS process technology in analog, digital, RF and SoC designs, including digitally-assisted techniques for data converters, DSP enabled frequency synthesizers, and digital controllers for switching power converters. With detailed descriptions, explanations, and practical advice from leading industry experts, this is an ideal resource for practicing engineers, researchers, and graduate students working in circuit design.

Clock Generators for SOC Processors
Clock Generators for SOC Processors

Author: Amr Fahim

Publisher: Springer Science & Business Media

Published: 2005-12-06

Total Pages: 257

ISBN-13: 1402080808

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This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.

Reconfigurable Logic
Reconfigurable Logic

Author: Pierre-Emmanuel Gaillardon

Publisher: CRC Press

Published: 2018-09-03

Total Pages: 526

ISBN-13: 1482262193

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During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields. Field programmable gate arrays (FPGAs) are one of the most famous architecture families of reconfigurable devices. FPGAs can be seen as arrays of logic units that can be reconfigured to realize any digital systems. Their high versatility has enabled designers to drastically reduce time to market, and made FPGAs suitable for prototyping or small production series in many branches of industrial products. In addition, and thanks to innovations at the architecture level, FPGAs are now conquering segments of mass markets such as mobile communications. Reconfigurable Logic: Architecture, Tools, and Applications offers a snapshot of the state of the art of reconfigurable logic systems. Covering a broad range of architectures, tools, and applications, this book: Explores classical FPGA architectures and their supporting tools Evaluates recent proposals related to FPGA architectures, including the use of network-on-chips (NoCs) Examines reconfigurable processors that merge concepts borrowed from the reconfigurable domain into processor design Exploits FPGAs for high-performance systems, efficient error correction codes, and high-bandwidth network routers with built-in security Expounds on emerging technologies to enhance FPGA architectures, improve routing structures, and create non-volatile configuration flip-flops Reconfigurable Logic: Architecture, Tools, and Applications reviews current trends in reconfigurable platforms, providing valuable insight into the future potential of reconfigurable systems.

Design of High-speed Communication Circuits
Design of High-speed Communication Circuits

Author: Ramesh Harjani

Publisher: World Scientific

Published: 2006

Total Pages: 233

ISBN-13: 9812565906

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MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible.The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O.

Noise Coupling in System-on-Chip
Noise Coupling in System-on-Chip

Author: Thomas Noulis

Publisher: CRC Press

Published: 2018-01-09

Total Pages: 555

ISBN-13: 1351642782

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Noise Coupling is the root-cause of the majority of Systems on Chip (SoC) product fails. The book discusses a breakthrough substrate coupling analysis flow and modelling toolset, addressing the needs of the design community. The flow provides capability to analyze noise components, propagating through the substrate, the parasitic interconnects and the package. Using this book, the reader can analyze and avoid complex noise coupling that degrades RF and mixed signal design performance, while reducing the need for conservative design practices. With chapters written by leading international experts in the field, novel methodologies are provided to identify noise coupling in silicon. It additionally features case studies that can be found in any modern CMOS SoC product for mobile communications, automotive applications and readout front ends.

High Performance Memory Testing
High Performance Memory Testing

Author: R. Dean Adams

Publisher: Springer Science & Business Media

Published: 2005-12-29

Total Pages: 252

ISBN-13: 0306479729

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Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Silicon Heterostructure Handbook
Silicon Heterostructure Handbook

Author: John D. Cressler

Publisher: CRC Press

Published: 2018-10-03

Total Pages: 1248

ISBN-13: 1420026585

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An extraordinary combination of material science, manufacturing processes, and innovative thinking spurred the development of SiGe heterojunction devices that offer a wide array of functions, unprecedented levels of performance, and low manufacturing costs. While there are many books on specific aspects of Si heterostructures, the Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits, and Applications of SiGe and Si Strained-Layer Epitaxy is the first book to bring all aspects together in a single source. Featuring broad, comprehensive, and in-depth discussion, this handbook distills the current state of the field in areas ranging from materials to fabrication, devices, CAD, circuits, and applications. The editor includes "snapshots" of the industrial state-of-the-art for devices and circuits, presenting a novel perspective for comparing the present status with future directions in the field. With each chapter contributed by expert authors from leading industrial and research institutions worldwide, the book is unequalled not only in breadth of scope, but also in depth of coverage, timeliness of results, and authority of references. It also includes a foreword by Dr. Bernard S. Meyerson, a pioneer in SiGe technology. Containing nearly 1000 figures along with valuable appendices, the Silicon Heterostructure Handbook authoritatively surveys materials, fabrication, device physics, transistor optimization, optoelectronics components, measurement, compact modeling, circuit design, and device simulation.