Author: Kenneth Hoi Kan Yau

Publisher:

Published: 2011

Total Pages: 472

ISBN-13: 9780494780619

This thesis presents the theoretical and experimental framework for the development of accurate on-wafer S-parameter and noise parameter measurements of silicon devices in the upper millimetre-wave frequency range between 70 GHz and 300 GHz. Novel integrated noise parameter test setups were developed for nanoscale MOSFETs and SiGe HBTs and validated up to 170 GHz. In the absence of accurate foundry models in this frequency range, the experimental findings of this thesis have been employed by other graduate students to design the first noise and input impedance matched W- and D -band low-noise amplifiers in nanoscale CMOS and SiGe BiCMOS technologies. The results of the D-band S-parameter characterization techniques and of the new Y-parameter based noise model have been used by STMicroelectronics to optimize the SiGe HBT structure for applications in the D-band.Finally, to validate the proposed noise model, the first on-wafer integrated noise parameter measurement systems were designed and measured in the W- and D-bands. The systems enable millimetre-wave noise parameter measurements with the multi-impedance method by integrating the impedance tuner and an entire millimetre-wave noise receiver on the same die as the device-under-test. Good agreement was obtained between the noise parameters calculated from the Y-parameter measurements and those obtained from direct noise figure measurements with the integrated systems. The results indicate that the minimum noise figure of state-of-the-art advanced SiGe HBTs remains below 5 dB throughout the D-band, making them suitable for a variety of commercial products in this frequency range.In the first half of the thesis, theoretical analysis indicates that, for current silicon devices, distributive effects in test structure parasitics will become significant only beyond 300 GHz. This conclusion is supported by experiments which compare the lumped-element based open-short and the transmission line based split-thru de-embedding techniques to the multiline thru-reflect-line (TRL) network analyzer calibration algorithm.Electromagnetic simulations and measurements up to 170 GHz demonstrate that, for microstrip transmission lines with metal ground plane placed above the silicon substrate, the line capacitance per unit length remains a weak function of frequency. Based on this observation, the multiline TRL algorithm has been modified to include a dummy short de-embedding structure. This allowed for the first time to perform single step calibration and de-embedding of silicon devices using on-silicon calibration standards. The usefulness of the proposed method was demonstrated on the extraction of the difficult-to-measure SiGe HBT and nanoscale MOSFET model parameters, including transcondutance delay, tau, gate resistance, source resistance, drain-source capacitance, and channel resistance, Ri.Building on the small-signal characterization technique developed in the first half, a new Y-parameter based noise model for SiGe HBTs, that includes the correlation between the base and collector shot noise currents, is proposed in the second half of the thesis along with a method to extract the noise transit time parameter. With this model, the high frequency noise parameters of a SiGe HBT can be calculated from the measured Y-parameters, without requiring any noise figure measurements.