The suppression work proposes active noise cancellation structures that can be used in addition to conventional guard ring methods. Coupling reduction for NMOS in common-source amplifier of 8.8 times has been achieved at 10 MHz sinusoidal substrate noise. Coupling reduction for NMOS common source with degeneration of 56 times has been achieved at 10 MHz. Ring oscillator sideband suppression of 25 dB has been achieved at 1 MHz sinusoidal substrate noise for differential delay cells with noise cancellation.
This book is the first in a series of three dedicated to advanced topics in Mixed-Signal IC design methodologies. It is one of the results achieved by the Mixed-Signal Design Cluster, an initiative launched in 1998 as part of the TARDIS project, funded by the European Commission within the ESPRIT-IV Framework. This initiative aims to promote the development of new design and test methodologies for Mixed-Signal ICs, and to accelerate their adoption by industrial users. As Microelectronics evolves, Mixed-Signal techniques are gaining a significant importance due to the wide spread of applications where an analog front-end is needed to drive a complex digital-processing subsystem. In this sense, Analog and Mixed-Signal circuits are recognized as a bottleneck for the market acceptance of Systems-On-Chip, because of the inherent difficulties involved in the design and test of these circuits. Specially, problems arising from the use of a common substrate for analog and digital components are a main limiting factor. The Mixed-Signal Cluster has been formed by a group of 11 Research and Development projects, plus a specific action to promote the dissemination of design methodologies, techniques, and supporting tools developed within the Cluster projects. The whole action, ending in July 2002, has been assigned an overall budget of more than 8 million EURO.
Trends toward portable electronics are leading forces in developing new systems. Accordingly, two features have become crucial in implementing these integrated systems: wireless communication and efficiency in size and energy consumption. Efforts to facilitate both digital and analog features produce mixed signal System-On-Chip (SOC), which include both analog and digital functions on a single die. Noise coupling in such an environment is a key issue in improving system performance; in particular, the noise coupling through the common substrate (i.e. substrate noise) is unavoidable as physical separation between the functions shrinks with technology scaling. To prevent the system performance from degenerating due to the substrate noise, methodologies for analyzing, estimating and measuring the noise in both simulated and practical conditions are essential and worthy of full investigation. This dissertation has conducted such an investigation in mixed signal SOCs Overall, this dissertation presents methodologies regarding how to understand, estimate, and measure the substrate noise in the mixed-signal SOC. As long as mixed-signal systems prevail in the integrated electronics industry, the SOC as well as the SIP should become the main frames of system implementations, and the presented research can contribute to shaping these frames.
Strategies for simulation and measurement of substrate noise have been analyzed using various digital and analog circuits fabricated in the TSMC 0.35um heavily doped CMOS process. The measurements validate a substrate noise coupling macromodel that has been used to obtain the simulation results. The simulations and measurements also substantiate the effectiveness of various noise suppression techniques. Additionally, strategies for simulation and measurement have been extended and circuits have been designed for verification of these strategies in the IBM 7HP 0.18um lightly doped BiCMOS process.
A new method is presented to compress switching information in large digital circuits. This is combined with an efficient approach of generating the noise signatures of cells in a digital library that results in an accurate and efficient approach for estimating the noise generated in digital circuits. This method provides a practical approach to generating the digital switching noise for simulating substrate coupling noise in mixed-signal ICs. Orders of magnitude reduction in the memory and simulation time are achieved using this approach without significant loss of accuracy.
Switching noise generated by digital circuits can degrade analog circuit performance in mixed-signal integrated circuits (ICs). In an analog-to-digital converter (ADC), one major source of switching noise is digital output buffers. Traditional methods for mitigating this problem mostly have been to try to isolate the digital noise to reduce coupling into sensitive nodes. This dissertation presents two fully digital and adaptive algorithms, which find and cancel errors due to switching noise coupling at the output of an ADC without noise sensors. To demonstrate the operation of this algorithm, a 12-bit, 40-MS/s pipelined ADC has been designed and fabricated in 0.18-um CMOS process. The system consists of an ADC with its own output buffers, and eight other independent digital output buffers (noise buffers), which can be programmed to produce four different kinds of switching noise. The switching noise cancellation (SNC) algorithms estimate noise parameters in the ADC and store them in lookup tables implemented as RAMs. If the outputs of a digital noise source are known, the use of RAM eliminates the need for analog noise sensors, and scaling in advanced technologies reduces the cost of integrated memory. At the ADC output, the effects of switching noise is digitally removed to recover the input samples. Measured results show that the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 64.9 dB without any of the noise buffers on. With the noise buffers on, the worst-case SNDR before and after SNC is 51.9 dB and 63.7 dB, respectively.
Abstract: "We describe a set of placement algorithms for handling substrate-coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first-cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate-noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macro-cells. A simple technique for characterizing these models is also presented. The digital/analog interactions determined through these models are incorporated into a simulated annealing macro-cell placement framework. Automatic placement results indicate these substrate-aware algorithms allow efficient mixed- signal placement optimization."
Noise cancellation is particularly important in the new mobile communications field, with respect to background noise and acoustic interference in moving vehicles. This comprehensive text develops a coherent and structured presentation of a broad range of the theory and application of statistical signal processing, with emphasis on digital noise reduction algorithms. Other applications covered are spectral estimation, channel equalisation, speech coding over noisy channels, speech recognition in adverse environments, active noise control, echo cancellation, restoration of lost filters, and adaptive notch filters.
