This book covers issues and solutions in the physical integration and tapeout management for VLSI design. Chapter 1 gives the overview. Chapter 2 shows detailed techniques for physical design. Chapter 3 provides CAD flows. Chapter 4 discusses on-chip interconnects. A glossary of keywords is provided at the end.
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. "VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.
This practical, tool-independent guide to designing digital circuits takes a unique, top-down approach, reflecting the nature of the design process in industry. Starting with architecture design, the book comprehensively explains the why and how of digital circuit design, using the physics designers need to know, and no more.
With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip (SoC) has become an essential technique to reduce product cost. With this progress and continuous reduction of feature sizes, and the development of very large-scale integration (VLSI) circuits, addressing the harder problems requires fundamental understanding
The Complete, Modern Tutorial on Practical VLSI Chip Design, Validation, and Analysis As microelectronics engineers design complex chips using existing circuit libraries, they must ensure correct logical, physical, and electrical properties, and prepare for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design. Microprocessor design authority Tom Dillinger carefully introduces core concepts, and then guides engineers through modeling, functional design validation, design implementation, electrical analysis, and release to manufacturing. Writing from the engineer’s perspective, he covers underlying EDA tool algorithms, flows, criteria for assessing project status, and key tradeoffs and interdependencies. This fresh and accessible tutorial will be valuable to all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. Reflect complexity, cost, resources, and schedules in planning a chip design project Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements Model functionality and behavior, validate designs, and verify formal equivalency Apply EDA tools for logic synthesis, placement, and routing Analyze timing, noise, power, and electrical issues Prepare for manufacturing release and bring-up, from mastering ECOs to qualification This guide is for all VLSI system designers, senior undergraduate or graduate students of microelectronics design, and companies offering internal courses for engineers at all levels. It is applicable to engineering teams undertaking new projects and migrating existing designs to new technologies.
"Physical Design of CMOS Integrated Circuits Using L-Edit is the first book/software package that enables engineering students and professionals to perform full IC layout on an inexpensive personal computer. The Student Version of L-Edit, included with the book on a 3.5-inch disk, is a full-featured layout editor that runs on MS-DOS compatible computers with minimal hardware requirements (640K RAM, a mouse, and an EGA or better color monitor). L-Edit allows the user to implement the physical design of an integrated circuit at the silicon level, and provides output for circuit simulation on SPICE. The entire process of chip design - once the exclusive province of workstation-based CAD systems - can now be performed on a PC." "Database files for many standard MOSIS CMOS processes are provided on disk, including Orbit and HP 2.0 and 1.2-micron technology base definitions. The program provides for circuit extraction (translating the layout to a SPICE-compatible text file), and design rule checking using predefined MOSIS rules or custom-designed sets. It also features a unique cross-sectional viewer that constructs the side view layering from the layoutthis viewer helps users visualize the link between layout drawings and the device structure. Circuit designs created on the Student Version of L-Edit can be translated to GDS II or CIF format for submission to a fabrication foundry using the Professional Version of L-Edit."--BOOK JACKET.Title Summary field provided by Blackwell North America, Inc. All Rights Reserved
This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems.
Now in a thoroughly revised second edition, this practical practitioner guide provides a comprehensive overview of the SoC design process. It explains end-to-end system on chip (SoC) design processes and includes updated coverage of design methodology, the design environment, EDA tool flow, design decisions, choice of design intellectual property (IP) cores, sign-off procedures, and design infrastructure requirements. The second edition provides new information on SOC trends and updated design cases. Coverage also includes critical advanced guidance on the latest UPF-based low power design flow, challenges of deep submicron technologies, and 3D design fundamentals, which will prepare the readers for the challenges of working at the nanotechnology scale. A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide, Second Edition provides engineers who aspire to become VLSI designers with all the necessary information and details of EDA tools. It will be a valuable professional reference for those working on VLSI design and verification portfolios in complex SoC designs