This book provides insight into the behavior and design of power distribution systems for high speed, high complexity integrated circuits. Also presented are criteria for estimating minimum required on-chip decoupling capacitance. Techniques and algorithms for computer-aided design of on-chip power distribution networks are also described; however, the emphasis is on developing circuit intuition and understanding the principles that govern the design and operation of power distribution systems.
This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.
"A critical challenge in high performance nanoscale integrated circuits is high quality power delivery. The efficient generation and distribution of multiple on-chip power supply voltages require fundamental changes to the power delivery process to provide increased current in next generation nanoscale integrated circuits. Four primary components are required to realize an efficient power delivery system: (a) ultra-small voltage converters to generate power close to the load, (b) accurate models to characterize the individual power components, (c) efficient algorithms to analyze the quality of the power delivered to the load circuits, and (d) a co-design methodology to simultaneously determine the optimal location of the on-chip power supplies and decoupling capacitors. In this dissertation, a hybrid combination of a switching and low-dropout (LDO) regulator as a point-of-load power supply for next generation heterogeneous systems is proposed. The area of this circuit is significantly smaller than the area of conventional voltage regulators, while maintaining high current efficiency. The proposed circuit provides a means for distributing multiple local power supplies across an integrated circuit. Another important challenge in the realization of effective power delivery systems is the analysis of this highly complicated structure where individual voltage fluctuations at millions of nodes need to be efficiently determined. Closed-form expressions for the effective resistance between circuit components have been developed. This effective resistance model is utilized in the development of a power grid analysis algorithm to compute the node voltages without requiring any iterations. This algorithm drastically improves computational complexity since the iterative procedures to determine IR drop and L di/dt noise are no longer needed. With the introduction of ultra-small on-chip voltage regulators, there is a need for novel design methodologies to determine the location of these on-chip power supplies and decoupling capacitors. A co-design methodology is proposed to simultaneously determine the optimal location of the power supplies and decoupling capacitors within a high performance power delivery network. Optimization algorithms widely used for facility location problems are applied in the proposed methodology. The effects of the size, number, and location of the power supplies and decoupling capacitors on the power noise are also discussed"--Page ix-x.
The latest techniques for designing robust, high performance integrated circuits in nanoscale technologies Focusing on a new technological paradigm, this practical guide describes the interconnect-centric design methodologies that are now the major focus of nanoscale integrated circuits (ICs). High Performance Integrated Circuit Design begins by discussing the dominant role of on-chip interconnects and provides an overview of technology scaling. The book goes on to cover data signaling, power management, synchronization, and substrate-aware design. Specific design constraints and methodologies unique to each type of interconnect are addressed. This comprehensive volume also explains the design of specialized circuits such as tapered buffers and repeaters for data signaling, voltage regulators for power management, and phase-locked loops for synchronization. This is an invaluable resource for students, researchers, and engineers working in the area of high performance ICs. Coverage includes: Technology scaling Interconnect modeling and extraction Signal propagation and delay analysis Interconnect coupling noise Global signaling Power generation Power distribution networks CAD of power networks Techniques to reduce power supply noise Power dissipation Synchronization theory and tradeoffs Synchronous system characteristics On-chip clock generation and distribution Substrate noise in mixed-signal ICs Techniques to reduce substrate noise
This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.
Miniaturization of electronic products due to the current trend in the electronics industry has led to the integration of components within the chip and package. Traditionally, individual decoupling capacitors placed on the surface of the board or the package have been used to decouple active switching circuits. However, with an increase in the clock rates and its harmonics with technology nodes, decoupling has to be provided in the GHz range. Discrete decoupling capacitors are no longer effective in this region because of the increased inductive effects of the current paths of the capacitors, which limits its effectiveness in the tens of MHz range. The use of embedded individual thick film capacitors within the package is a feasible solution for decoupling core logic above 100 MHz. They overcome the limitations of SMDs (Surface Mount Discretes), primarily in decoupling active circuits in the mid-frequency band. Inclusion of embedded planar capacitors in the board stack up have shown improvements in the overall impedance profile and have shown to exhibit better noise performance. The main contributor to the superior performance is the reduced inductive effects of the power-ground planes because of the thinner dielectrics of the embedded capacitor. The modeling, measurement and characterization of embedded decoupling capacitors in the design of PDNs (Power Distribution Networks) has been investigated in this thesis.
Wafer-scale integration has long been the dream of system designers. Instead of chopping a wafer into a few hundred or a few thousand chips, one would just connect the circuits on the entire wafer. What an enormous capability wafer-scale integration would offer: all those millions of circuits connected by high-speed on-chip wires. Unfortunately, the best known optical systems can provide suitably ?ne resolution only over an area much smaller than a whole wafer. There is no known way to pattern a whole wafer with transistors and wires small enough for modern circuits. Statistical defects present a ?rmer barrier to wafer-scale integration. Flaws appear regularly in integrated circuits; the larger the circuit area, the more probable there is a ?aw. If such ?aws were the result only of dust one might reduce their numbers, but ?aws are also the inevitable result of small scale. Each feature on a modern integrated circuit is carved out by only a small number of photons in the lithographic process. Each transistor gets its electrical properties from only a small number of impurity atoms in its tiny area. Inevitably, the quantized nature of light and the atomic nature of matter produce statistical variations in both the number of photons de?ning each tiny shape and the number of atoms providing the electrical behavior of tiny transistors. No known way exists to eliminate such statistical variation, nor may any be possible.
This book covers the state-of-the-art research in design of modern electronic systems used in safety-critical applications such as medical devices, aircraft flight control, and automotive systems. The authors discuss lifetime reliability of digital systems, as well as an overview of the latest research in the field of reliability-aware design of integrated circuits. They address modeling approaches and techniques for evaluation and improvement of lifetime reliability for nano-scale CMOS digital circuits, as well as design algorithms that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. In addition to developing lifetime reliability analysis and techniques for clocked storage elements (such as flip-flops), the authors also describe analysis and improvement strategies targeting commercial digital circuits.
