This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.
Increased design complexity and time-to-market pressure in the integrated circuit (IC) industry call for a raised level of abstraction at which designs are specified. High-level synthesis is the process of generating register-transfer level (RTL) implementations from behavioral specifications, and it is the key enabler for a designing at a higher level beyond RTL. As IC manufacturing technology scales down to nanoscopic scale, the synthesis tools face a number of new challenges, including complexity, power and interconnect. In this dissertation, we propose a spectrum of new techniques in high-level synthesis to address the new challenges and to improve the quality of synthesis results. 1. Efficient and versatile scheduling engine using soft constraints. We present a scheduler that distinguishes soft constraints from hard constraints when exploring the design space, and identify a class of tractable scheduling problems with soft constraints. By exploiting the total unimodularity of the constraint matrix in an integer-linear programming formulation, we are able to solve the problem optimally in polynomial time. Compared to traditional methods, the proposed approach allows easier expression of various design intentions and optimization directions, and, at the same time, gives the scheduler freedom to make global trade-offs optimally. We show that this scheduling engine is flexible enough to support a variety of design considerations in high-level synthesis. 2. Behavior-level observability analysis and power optimization. We introduce the concept of behavior-level observability and its approximations in the context of high-level synthesis, and propose an efficient procedure to compute an approximated behavior-level observability of every operation in a dataflow graph. The algorithm exploits the observability-masking nature of some Boolean operations, as well as the select operation, and treats other operations as black boxes to allow efficient word-level analysis. The result is proven to be exact under the black-box abstraction. The behavior-level observability condition obtained by our analysis can be used to optimize operation gating in the scheduler. This leads to more opportunities in subsequent RTL synthesis for power reduction. To the best of our knowledge, this is the first time behavior-level observability analysis and optimization are performed in a systematic manner. 3. Layout-friendly high-level synthesis. We study a number of structural metrics for measuring the layout-friendliness of microarchitectures generated in high-level synthesis. For a piece of connected netlist, we introduce the spreading score to measures how far components can be spread from each other with bounded wire length in a graph embedding formulation. The intuition is that components in a layout-friendly netlist (e.g., a mesh) can spread over the layout region without introducing long interconnects. Spreading score can be approximated efficiently using a semidefinite programming relaxation. Another metric based on neighborhood population is also proposed. On a number of benchmarks, spreading score shows stronger bias in favor of interconnect structures that have shorter wire length after layout, compared to previous metrics based on cut size and total multiplexer inputs.
ABSTRACT: Aggressive scaling of nanoscale CMOS integrated circuits has created significant design challenges arising from increasing power densities, thermal concerns, and rising wire delays. The main contribution of this dissertation is the development of unified physical and high-level synthesis techniques for the design of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power consumption, and cooling costs. To address this, we present a temperature-aware behavioral synthesis (TABS) framework that combines power minimization with temperature-aware task scheduling, resource binding, and floorplanning. Compared to conventional low-power synthesis methods, our approach is effective in synthesizing circuits with lower chip temperatures and more uniform thermal distributions, with temperature reductions up to 23% when compared to low-power synthesis. We propose three techniques to address interconnect delays during high-level synthesis: (1) a simulated annealing (SA) based layout-aware high-level synthesis technique for 3-D integrated circuits, that tightly couples the synthesis tasks of resource binding and 3-D floorplanning. The proposed algorithm significantly outperforms a conventional synthesis flow that separates the binding and floorplanning steps, with improvements in the total wirelength by 29% and of the longest wirelength by 21%; (2) a floorplan-aware high-level synthesis technique that uses the topology of multi-terminal nets to improve interconnect delay estimates during resource binding. Experiments show that the use of accurate wire delay estimates during binding can reduce wire delays by as much as 49% in 70nm technology; (3) an iterative high-level design-space exploration engine that uses a priori stochastic wirelength estimates to guide binding decisions during high-level synthesis. The proposed approach offers a significant speed-up during design space exploration when compared to approaches that use traditional place-and-route to evaluate candidate solutions. Finally, we present a genetic algorithm (GA) based approach for high-level synthesis. We propose novel GA encoding, crossover, and mutation operators for the problem. The quality of the results generated by the GA are superior to those of several other techniques reported in the literature.
This book describes methodologies in the design of VLSI devices, circuits and their applications at nanoscale levels. The book begins with the discussion on the dominant role of power dissipation in highly scaled devices.The 15 Chapters of the book are classified under four sections that cover design, modeling, and simulation of electronic, magnetic and compound semiconductors for their applications in VLSI devices, circuits, and systems. This comprehensive volume eloquently presents the design methodologies for ultra–low power VLSI design, potential post–CMOS devices, and their applications from the architectural and system perspectives. The book shall serve as an invaluable reference book for the graduate students, Ph.D./ M.S./ M.Tech. Scholars, researchers, and practicing engineers working in the frontier areas of nanoscale VLSI design.
This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. It includes an overview of available EDA tool solutions and their applicability to design problems.
This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided. FEATURES Discusses the latest updates in the field of ultra low power semiconductor transistors Provides both experimental and analytical solutions for TFETs and NCFETs Presents synthesis and fabrication processes for FinFETs Reviews details on 2-D materials and 2-D transistors Explores the application of FETs for biosensing in the healthcare field This book is aimed at researchers, professionals, and graduate students in electrical engineering, electronics and communication engineering, electron devices, nanoelectronics and nanotechnology, microelectronics, and solid-state circuits.
This books focuses on recent break-throughs in the development of a variety of photonic devices, serving distances ranging from mm to many km, together with their electronic counter-parts, e.g. the drivers for lasers, the amplifiers following the detectors and most important, the relevant advanced VLSI circuits. It explains that as a consequence of the increasing dominance of optical interconnects for high performance workstation clusters and supercomputers their complete design has to be revised. This book thus covers for the first time the whole variety of interdependent subjects contributing to green photonics and electronics, serving communication and energy harvesting. Alternative approaches to generate electric power using organic photovoltaic solar cells, inexpensive and again energy efficient in production are summarized. In 2015, the use of the internet consumed 5-6% of the raw electricity production in developed countries. Power consumption increases rapidly and without some transformational change will use, by the middle of the next decade at the latest, the entire electricity production. This apocalyptic outlook led to a redirection of the focus of data center and HPC developers from just increasing bit rates and capacities to energy efficiency. The high speed interconnects are all based on photonic devices. These must and can be energy efficient but they operate in an electronic environment and therefore have to be considered in a wide scope that also requires low energy electronic devices, sophisticated circuit designs and clever architectures. The development of the next generation of high performance exaFLOP computers suffers from the same problem: Their energy consumption based on present device generations is essentially prohibitive.
This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006. The book presents 41 revised full papers and 23 revised poster papers together with 4 key notes and 3 industrial abstracts. Topical sections include high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, and more.
