FPGA Logic Design for Analog-to-digital-converter Hardware Utilizing High Speed Serial Data Links
FPGA Logic Design for Analog-to-digital-converter Hardware Utilizing High Speed Serial Data Links

Author:

Publisher:

Published: 2006

Total Pages: 53

ISBN-13:

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The Computer Assisted Dynamic Data Monitoring and Analysis System (CADDMAS) used by the aeropropulsion test cells at Arnold Engineering Development Center (AEDC) processes a large amount of high bandwidth accelerometer and strain gage data. Data from each sensor must be digitized before being processed by software running on networked computers. This thesis describes some of the original analog-todigital converter (ADC) hardware used by the CADDMAS as well as some of its limitations. More up-to-date ADC hardware was designed to be used in the CADDMAS to enhance capabilities required by the aeropropulsion test cells. These new capabilities included an increase in maximum sample rate for the CADDMAS, a Universal Serial Bus (USB) 2.0 interface for easy connection to the computer, the latest Field Programmable Gate Arrays (FPGAs) for controlling the data acquisition, and a packet based data transmission scheme to reduce redundant data transfers into the computer. This thesis describes, in detail, the development and checkout of the FPGA logic for the new ADC hardware needed to obtain these enhanced capabilities. A simple software program was also developed to validate the correct operation of the new ADC hardware and to demonstrate to a commercial software vendor how to incorporate support for the ADC hardware into their software. Upon completion of the designs, a maximum data transfer rate of 96.15 Megabytes per second (MBps) was obtained using a PCI interface card and 18.45 MBps was obtained from the USB 2.0 interface.

FPGA to High speed ADC Data streaming
FPGA to High speed ADC Data streaming

Author: Marco Gottardo

Publisher: Lulu.com

Published: 2018

Total Pages: 218

ISBN-13: 0244366896

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Where does the content of this book apply? Firstly in research institutes where it is necessary to acquire data in streaming at high speed and low noise especially in the lower part of the spectrum. For example the current machines for the study of nuclear fusion does not produce energy, and their output is substantially a large amount of data. The accuracy of the data collected, and their density within narrow temporal samples, can determine the effectiveness of the real time control systems to install in future reactors. We set ourselves the objective to design and test a high-speed and high-density data acquisition system based on the latest generation FPGA technologies. in the book is used the latest products released by Xilinx to design a acquire stream system of signals from generic probes (specifically magnetic probes). The Zynq 7000 family is nowadays state of the art of sistemy SoC that integrating a powerful and extensive FPGA section with an ARM mullticore.

Design and Modeling of an Analog to Digital Converter Using Field Programmable Gate Array Board
Design and Modeling of an Analog to Digital Converter Using Field Programmable Gate Array Board

Author: Riayad M. Herwies

Publisher:

Published: 2013

Total Pages: 86

ISBN-13:

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In this project the design and modeling of an analog to digital converter using a field programming gate array (FPGA) board is presented. The FPGA contains digital components that make it possible to implement a digital ADC. The simulation is done using Xilinx Spartan 3E board and a hardware description language VHDL is used to design and simulate different ways of implementing a Single-Slope ADC; each has its pros and cons in terms of speed and resolution. By using different parameters to implement the Single-Slope ADC, the authors seek to find out the possibility of achieving different speed and resolution of the digital ADC. First the analog input signal is fed to the FPGA through low voltage differential signaling pins (LVDS) that are available in most of the FPGAs. The signal is processed and converted inside the FPGA to a digital form. The output of the FPGA is sent to a low pass filter in order to convert the signal back to analog and used as a reference voltage.

Data Converters, Phase-Locked Loops, and Their Applications
Data Converters, Phase-Locked Loops, and Their Applications

Author: Tertulien Ndjountche

Publisher: CRC Press

Published: 2018-09-06

Total Pages: 480

ISBN-13: 0429939043

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With a focus on designing and verifying CMOS analog integrated circuits, the book reviews design techniques for mixed-signal building blocks, such as Nyquist and oversampling data converters, and circuits for signal generation, synthesis, and recovery. The text details all aspects, from specifications to the final circuit, of the design of digital-to-analog converters, analog-to-digital converters, phase-locked loops, delay-locked loops, high-speed input/output link transceivers, and class D amplifiers. Special emphasis is put on calibration methods that can be used to compensate circuit errors due to device mismatches and semiconductor process variations. Gives an overview of data converters, phase- and delay-locked loop architectures, highlighting basic operation and design trade-offs. Focus on circuit analysis methods useful to meet requirements for a high-speed and power-efficient operation. Outlines design challenges of analog integrated circuits using state-of-the-art CMOS processes. Presents design methodologies to optimize circuit performance on both transistor and architectural levels. Includes open-ended circuit design case studies.

Data Conversion Handbook
Data Conversion Handbook

Author: Walt Kester

Publisher: Newnes

Published: 2005

Total Pages: 977

ISBN-13: 0750678410

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This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician

Applied Digital Logic Exercises Using FPGAs
Applied Digital Logic Exercises Using FPGAs

Author: Kurt Wick

Publisher: Morgan & Claypool Publishers

Published: 2017-10-03

Total Pages: 190

ISBN-13: 1681746638

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FPGAs have almost entirely replaced the traditional Application Specific Standard Parts (ASSP) such as the 74xx logic chip families because of their superior size, versatility, and speed. For example, FPGAs provide over a million fold increase in gates compared to ASSP parts. The traditional approach for hands-on exercises has relied on ASSP parts, primarily because of their simplicity and ease of use for the novice. Not only is this approach technically outdated, but it also severely limits the complexity of the designs that can be implemented. By introducing the readers to FPGAs, they are being familiarized with current digital technology and the skills to implement complex, sophisticated designs. However, working with FGPAs comes at a cost of increased complexity, notably the mastering of an HDL language, such as Verilog. Therefore, this book accomplishes the following: first, it teaches basic digital design concepts and then applies them through exercises; second, it implements these digital designs by teaching the user the syntax of the Verilog language while implementing the exercises. Finally, it employs contemporary digital hardware, such as the FPGA, to build a simple calculator, a basic music player, a frequency and period counter and it ends with a microprocessor being embedded in the fabric of the FGPA to communicate with the PC. In the process, readers learn about digital mathematics and digital-to-analog converter concepts through pulse width modulation.

Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters
Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters

Author: Sai-Weng Sin

Publisher: Springer Science & Business Media

Published: 2010-09-29

Total Pages: 147

ISBN-13: 9048197104

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Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.

FPGA Implementation of Robust Symmetrical Number System in High-speed Folding Analog-to-digital Converters
FPGA Implementation of Robust Symmetrical Number System in High-speed Folding Analog-to-digital Converters

Author: Han Wei Lim

Publisher:

Published: 2010

Total Pages: 105

ISBN-13:

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Analog-To-Digital Converters (ADCs) are integral building blocks of most sensor and communication systems today. As the need for ADCs with faster conversion speeds and lower power dissipation increases, there is a growing motivation to reduce the number of power-consuming components by employing folding circuits to fold the input analog signal symmetrically prior to quantization by high-speed comparators. These properties of low-power consumption, compactness, high-resolution and fast conversion speeds make folding ADCs an attractive concept to be used for defense applications, such as unmanned systems, direction-finding antenna architectures and system-on-a-chip applications. In this thesis, a prototype of an optical folding ADC was implemented using the Robust Symmetrical Number System (RSNS). The architecture employs a three-modulus (Moduli 7, 8, 9) scheme to preprocess the antenna signal. This thesis focuses on the simulation and hardware implementation of this ADC architecture, including the bank of comparators and the RSNS-to-Binary Conversion within a Field Programmable Gate Array (FPGA), to achieve an eight-bit dynamic range of 133. This is then integrated with the front-end photonics implementation (designed under a separate thesis). Low frequency analyses of the results using a 1-kHz input signal indicate a 5.39 Effective Number of Bits (ENOB), a Signal-to-Noise Ratio plus Distortion (SINAD) of 34.21 dB, and a Total Harmonic Distortion (THD) of -61.68 dB.

Design Features of a Transistorized, High Speed Analog-to-digital Converter.
Design Features of a Transistorized, High Speed Analog-to-digital Converter.

Author: Wade E Clarke

Publisher: Hassell Street Press

Published: 2023-07-18

Total Pages: 0

ISBN-13: 9781019361887

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Design Features of a Transistorized High Speed Analog-to-Digital Converter is a technical report that describes the design of a high-speed electronic device. The report includes detailed information on the circuitry and components used in the device, as well as performance data and design considerations. This work has been selected by scholars as being culturally important, and is part of the knowledge base of civilization as we know it. This work is in the "public domain in the United States of America, and possibly other nations. Within the United States, you may freely copy and distribute this work, as no entity (individual or corporate) has a copyright on the body of the work. Scholars believe, and we concur, that this work is important enough to be preserved, reproduced, and made generally available to the public. We appreciate your support of the preservation process, and thank you for being an important part of keeping this knowledge alive and relevant.

Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters
Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters

Author: Yida Duan

Publisher:

Published: 2015

Total Pages: 80

ISBN-13:

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Analog-to-Digital Converters (ADCs) serve as the interfaces between the analog natural world and the binary world of computer data. Due to this essential role, ADC circuits have been well studied over 40 years, and many problems associated with them have already been solved. However in recent years, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often greater than 40GS/s) time-interleaved ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. Although such ADCs can be used in high-speed electronic measurement equipment and radar systems, the recent driving force behind them is next generation 100Gbps/400Gbps fiber optical transceivers. These transceivers take advantage of ultra-high-speed ADCs and digital-signal-processors (DSPs) to enable ultra-high data-rate communications in long-haul networks (city-to-city, transcontinental, and transoceanic fiber links), metro networks (fibers that connect enterprises in metropolitan areas), and data centers (fiber links within data center infrastructures). At such high sampling rate, massively time-interleaved successive-approximation ADC (SAR ADC) architecture has emerged as the dominant solution due to its excellent power efficiency. Several recent works has demonstrated success in achieving high sampling rate. However, the sampling network has become the bottleneck that limits the input bandwidth in these ADCs. It is apparent that conventional switch-based track-and-hold (T&H) circuit cannot satisfy the >20GHz bandwidth requirement. In addition, it is unclear what the optimal interleaving configuration is. Each state-of-the-art design adopts a different interleaving configuration - from straightforward conventional 1-rank interleaving to 2-rank hierarchical sampling or even 3 ranks. How to partition interleaving factors among different ranks has not yet been investigated. Furthermore, asynchronous SAR sub-ADCs are often used in these designs to push the sampling rate even further. The well-known sparkle-code issues caused by comparator meta-stability in asynchronous SARs can significantly increase the Bit-Error-Rate (BER) of the transceivers unless power hungry error correction coding are implemented in the system. Although many works in the literature attempted to deal with the meta-stability in asynchronous SARs, the effectiveness of these approaches have not been fully demonstrated. In this thesis, I will first propose a new cascode-based T&H circuits to improve the ADC bandwidth beyond the limit of conventional switch-based T&H circuits. Then, a system design and optimization methodology of hierarchical time-interleaved sampling network is presented in the context of cascode T&H. To deal with sparkle-code issue in asynchronous SAR sub-ADCs, a new back-end meta-stability correction technique is employed. An extensive statistical analysis is provided to verify the correction algorithm can greatly reduce sparkle-code error-rates. To further demonstrate the effectiveness of the proposed circuits and techniques, two prototype ADCs have been implemented. The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.