FPGA Implementation of Robust Symmetrical Number System in High-speed Folding Analog-to-digital Converters
FPGA Implementation of Robust Symmetrical Number System in High-speed Folding Analog-to-digital Converters

Author: Han Wei Lim

Publisher:

Published: 2010

Total Pages: 105

ISBN-13:

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Analog-To-Digital Converters (ADCs) are integral building blocks of most sensor and communication systems today. As the need for ADCs with faster conversion speeds and lower power dissipation increases, there is a growing motivation to reduce the number of power-consuming components by employing folding circuits to fold the input analog signal symmetrically prior to quantization by high-speed comparators. These properties of low-power consumption, compactness, high-resolution and fast conversion speeds make folding ADCs an attractive concept to be used for defense applications, such as unmanned systems, direction-finding antenna architectures and system-on-a-chip applications. In this thesis, a prototype of an optical folding ADC was implemented using the Robust Symmetrical Number System (RSNS). The architecture employs a three-modulus (Moduli 7, 8, 9) scheme to preprocess the antenna signal. This thesis focuses on the simulation and hardware implementation of this ADC architecture, including the bank of comparators and the RSNS-to-Binary Conversion within a Field Programmable Gate Array (FPGA), to achieve an eight-bit dynamic range of 133. This is then integrated with the front-end photonics implementation (designed under a separate thesis). Low frequency analyses of the results using a 1-kHz input signal indicate a 5.39 Effective Number of Bits (ENOB), a Signal-to-Noise Ratio plus Distortion (SINAD) of 34.21 dB, and a Total Harmonic Distortion (THD) of -61.68 dB.

Symmetrical Residue-to-Binary Conversion Algorithm, Pipelined FPGA Implementation, and Testing Logic for Use in High-Speed Folding Digitizers
Symmetrical Residue-to-Binary Conversion Algorithm, Pipelined FPGA Implementation, and Testing Logic for Use in High-Speed Folding Digitizers

Author:

Publisher:

Published: 2005

Total Pages: 67

ISBN-13:

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The robust symmetrical number system (RSNS) can play a significant role in the reduction of encoding errors within a low-power folding analog-to-digital converter (ADC). A key part of this ADC design is the logic block that converts the symmetrical residues from each channel into a more convenient binary output. This thesis describes a robust symmetrical residue-to-binary conversion algorithm for moduli 1 7 m =, 2 8 m = and 3 9 m = (ADC dynamic range M = 126). Also described is a pipelined digital logic implementation for use in high speed programmable logic or application specific integrated circuits. To verify correct outputs of the robust symmetrical residue-to-binary conversion algorithm, a digital test circuit is described that generates the thermometer code (symmetrical residues) for the 3-channel ADC design.

Photonic Analog-to-digital Converters Preprocessing Using the Robust Symmetrical Number System for Direct Digitization of Antenna Signals
Photonic Analog-to-digital Converters Preprocessing Using the Robust Symmetrical Number System for Direct Digitization of Antenna Signals

Author: Kee Leong Tong

Publisher:

Published: 2010

Total Pages: 87

ISBN-13:

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The need to realize pervasive battlespace awareness is placing an increasing demand on the bandwidth and resolution performance of modern sensors, communication receivers and electronic warfare. Fundamental to realizing this demand is the omnipresent highspeed analog-to-digital converters. The need constantly exists for converters with lower power consumption. To reduce the number of power-consuming components, high-performance ADCs employ parallel configuration of analog folding circuits to symmetrically fold the input signal prior to quantization by high-speed comparators. In this thesis, a prototype of an optical folding 6-bit ADC utilizing a 7-bit preprocessing architecture was implemented using the Robust Symmetrical Number System (RSNS). The RSNS preprocessing architecture is a modular scheme in which the integer values within each modulus (comparator states), when considered together, change one at a time at the next position i.e. Gray-code property. MATLAB simulations are used to help determine the properties of the RSNS. These properties include the dynamic range (largest number of distinct consecutive vectors) and the location of the dynamic range within the number system. Since the waveform repeats every fundamental period, a method that reduces all indexes to the 'lowest common denominator' is developed to find the symmetrical residues of each channel. Using the symmetrical residues determined, the corresponding DC shifts on each waveform can be calculated. The architecture employs a three-modulus (mod 7, 8, 9) scheme to preprocess the antenna signal. Electro-optic modulation of the input signal to generate the required number of folds within the dynamic range was successfully carried out in the three-modulus realization using modulators with a small half-wave voltage. The detection output are carefully aligned and postprocessed before amplitude analyzing with a high-speed comparator circuit responsible for the sampling and quantization of the signal (designed under a separate thesis). Low frequency analysis of the results using a 1 kHz input signal indicate a 5.42 effective number of bits (ENOB), a signal-to-noise ratio plus distortion (SINAD) of 34.42 dB, and a total harmonic distortion (THD) of -- 62.84 dB.

A Robust Symmetrical Number System with Gray Code Properties for Applications in Signal Processing
A Robust Symmetrical Number System with Gray Code Properties for Applications in Signal Processing

Author: Ilker Aydin Akin

Publisher:

Published: 1997-09-01

Total Pages: 102

ISBN-13: 9781423566212

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A new symmetrical number system with applications in parallel signal processing is investigated. The Robust Symmetrical Number System (RSNS) is a modular system in which the integer values within each modulus, when considered together, change one at a time at the next position (Gray code properties). Although the observed dynamic range of the RSNS is somewhat less than the optimum symmetrical number system, the Gray code properties make it particularly attractive for folding analog-to-digital converters. With the RSNS, the encoding errors (due to comparator thresholds not being crossed simultaneously) are eliminated, as is the need for the corresponding interpolation signal processing (reduced complexity). Computer generated data is used to help determine the properties of the RSNS. These properties include the largest dynamic range (number of distinct consecutive vectors), and the position of the largest dynamic range within the system. The position of the maximum unambiguous dynamic range is also quantified. Least squares analysis of 2 and 3 moduli systems are used to formulate closed-form expressions for the dynamic range. To compare the advantages of the RSNS with previously published results, the transfer function of a 3 channel RSNS folding analog-to-digital converter architecture (m1 =3, m2 = 4, and m3 = 5) is numerically evaluated using SPICE.

An Analog Preprocessing Architecture for High-speed Analog-to-digital Conversion
An Analog Preprocessing Architecture for High-speed Analog-to-digital Conversion

Author: Jorge A. Esparza

Publisher:

Published: 1993

Total Pages: 155

ISBN-13:

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This thesis investigates the feasibility of implementing an analog- to-digital converter (ADC) based on a new symmetrical number system (SNS). This preprocessing architecture decomposes the analog amplitude analyzing function of an ADC into a number of sub-operations (moduli). Each sub-operation folds the analog signal with a folding period proportional to the value of the modulus. Through the use of the SNS encoding and recombining the results of the sub- operations, a definitive performance enhancement is achieved. The number of comparators required is reduced considerably, allowing more bandwidth to be used in the folding circuits. The overall design effort demonstrates a 9-bit design with a total of 23 comparators. SPICE simulations are developed and the performance demonstrated. Also identified are the areas in which further research is required.

An Analog Preprocessing Architecture for High-speed Analog-to-digital Conversion
An Analog Preprocessing Architecture for High-speed Analog-to-digital Conversion

Author: Jorge A. Esparza

Publisher:

Published: 1993

Total Pages: 0

ISBN-13:

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This thesis investigates the feasibility of implementing an analog- to-digital converter (ADC) based on a new symmetrical number system (SNS). This preprocessing architecture decomposes the analog amplitude analyzing function of an ADC into a number of sub-operations (moduli). Each sub-operation folds the analog signal with a folding period proportional to the value of the modulus. Through the use of the SNS encoding and recombining the results of the sub- operations, a definitive performance enhancement is achieved. The number of comparators required is reduced considerably, allowing more bandwidth to be used in the folding circuits. The overall design effort demonstrates a 9-bit design with a total of 23 comparators. SPICE simulations are developed and the performance demonstrated. Also identified are the areas in which further research is required.

FPGA-based Implementation of Signal Processing Systems
FPGA-based Implementation of Signal Processing Systems

Author: Roger Woods

Publisher: John Wiley & Sons

Published: 2017-05-01

Total Pages: 356

ISBN-13: 1119077958

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An important working resource for engineers and researchers involved in the design, development, and implementation of signal processing systems The last decade has seen a rapid expansion of the use of field programmable gate arrays (FPGAs) for a wide range of applications beyond traditional digital signal processing (DSP) systems. Written by a team of experts working at the leading edge of FPGA research and development, this second edition of FPGA-based Implementation of Signal Processing Systems has been extensively updated and revised to reflect the latest iterations of FPGA theory, applications, and technology. Written from a system-level perspective, it features expert discussions of contemporary methods and tools used in the design, optimization and implementation of DSP systems using programmable FPGA hardware. And it provides a wealth of practical insights—along with illustrative case studies and timely real-world examples—of critical concern to engineers working in the design and development of DSP systems for radio, telecommunications, audio-visual, and security applications, as well as bioinformatics, Big Data applications, and more. Inside you will find up-to-date coverage of: FPGA solutions for Big Data Applications, especially as they apply to huge data sets The use of ARM processors in FPGAs and the transfer of FPGAs towards heterogeneous computing platforms The evolution of High Level Synthesis tools—including new sections on Xilinx's HLS Vivado tool flow and Altera's OpenCL approach Developments in Graphical Processing Units (GPUs), which are rapidly replacing more traditional DSP systems FPGA-based Implementation of Signal Processing Systems, 2nd Edition is an indispensable guide for engineers and researchers involved in the design and development of both traditional and cutting-edge data and signal processing systems. Senior-level electrical and computer engineering graduates studying signal processing or digital signal processing also will find this volume of great interest.

Design of High Speed Folding and Interpolating Analog-to-digital Converter
Design of High Speed Folding and Interpolating Analog-to-digital Converter

Author: Yunchu Li

Publisher:

Published: 2004

Total Pages:

ISBN-13:

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High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F & I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F & I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F & I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35 ơm CMOS process to verify the ideas. The S/H and F & I ADC prototype is realized in 0.35 [mu]m double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.

Digitally Assisted Pipeline ADCs
Digitally Assisted Pipeline ADCs

Author: Boris Murmann

Publisher: Springer Science & Business Media

Published: 2007-05-08

Total Pages: 164

ISBN-13: 1402078404

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Digitally Assisted Pipeline ADCs: Theory and Implementation explores the opportunity to reduce ADC power dissipation by leveraging digital signal processing capabilities in fine line integrated circuit technology. The described digitally assisted pipelined ADC uses a statistics-based system identification technique as an enabling element to replace precision residue amplifiers with simple open-loop gain stages. The digital compensation of analog circuit distortion eliminates one key factor in the classical noise-speed-linearity constraint loop and thereby enables a significant power reduction. Digitally Assisted Pipeline ADCs: Theory and Implementation describes in detail the implementation and measurement results of a 12-bit, 75-MSample/sec proof-of-concept prototype. The Experimental converter achieves power savings greater than 60% over conventional implementations. Digitally Assisted Pipeline ADCs: Theory and Implementation will be of interest to researchers and professionals interested in advances of state-of-the-art in A/D conversion techniques.

Software-Defined Radio for Engineers
Software-Defined Radio for Engineers

Author: Alexander M. Wyglinski

Publisher: Artech House

Published: 2018-04-30

Total Pages: 375

ISBN-13: 1630814598

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Based on the popular Artech House classic, Digital Communication Systems Engineering with Software-Defined Radio, this book provides a practical approach to quickly learning the software-defined radio (SDR) concepts needed for work in the field. This up-to-date volume guides readers on how to quickly prototype wireless designs using SDR for real-world testing and experimentation. This book explores advanced wireless communication techniques such as OFDM, LTE, WLA, and hardware targeting. Readers will gain an understanding of the core concepts behind wireless hardware, such as the radio frequency front-end, analog-to-digital and digital-to-analog converters, as well as various processing technologies. Moreover, this volume includes chapters on timing estimation, matched filtering, frame synchronization message decoding, and source coding. The orthogonal frequency division multiplexing is explained and details about HDL code generation and deployment are provided. The book concludes with coverage of the WLAN toolbox with OFDM beacon reception and the LTE toolbox with downlink reception. Multiple case studies are provided throughout the book. Both MATLAB and Simulink source code are included to assist readers with their projects in the field.