If you need an in-depth understanding of the digital clock technologies used in building today's telecommunications networks, this authoritative and practical book is a smart choice. Providing you with critical details on the PLL (phase-locked Loop) technique for clock synchronization and generation, and the DDS (direct digital synthesizer) technique for clock generation, the book helps you achieve synchronization in high-speed networks and frequency stabilization in portable equipment.
Network synchronization deals with the distribution of time and frequency across a network of clocks often spread over a wide geographical area. The goal is to align (i.e. synchronize) the time and frequency scales of all clocks, by using the communication capacity of their interconnecting links. Network synchronization plays a central role in digital telecommunications as it determines the quality of most services offered by the network operator. However, the importance of network synchronization is often underestimated and how to solve quality-of-service degradation caused by synchronization difficulties can become problematical to all but a synchronization engineer. * Systematically covers a wide spectrum of both theoretical and practical topics * Features a clear and profound description of synchronous and asynchronous digital multiplexing (PDH, SDH), jitter and timing aspects of SDH networks * Expounds synchronization network principles and implementation issues, clock modelling, time and frequency measurement * Presents recent advances in telecommunications clock characterization and measurement If you are a system engineer, researcher, designer or postgraduate student searching for both the basics and an insight into more advanced areas currently under discussion then you will find Synchronization of Digital Telecommunications Networks an enlightening read. It will also prove to be a valuable sourcebook for senior undergraduates and technical personnel in telecommunications companies.
Synchronization is a critical function in digital communications; its failures may have catastrophic effects on the transmission system performance. Furthermore, synchronization circuits comprehend such a large part of the receiver hardware that their implementation has a substantial impact on the overall costs. For these reasons design engineers are particularly concerned with the development of new and more efficient synchronization structures. Unfortunately, the advent of digital VLSI technology has radically affected modem design rules, to a point that most analog techniques employed so far have become totally obsolete. Although digital synchronization methods are well established by now in the literature, they only appear in the form of technical papers, often concentrating on specific performance or implementation issues. As a consequence they are hardly useful to give a unified view of an otherwise seemingly heterogeneous field. It is widely recognized that a fundamental understanding of digital synchronization can only be reached by providing the designer with a solid theoretical framework, or else he will not know where to adjust his methods when he attempts to apply them to new situations. The task of the present book is just to develop such a framework.
Today’s networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first. Current developments in integrated circuit processing are leading to an increase in the numbers of independent digital processing elements in a single system. With this comes faster communications, more networks on chip, and the demand for more reliable, more complex, and higher performance synchronizers and arbiters. Written by one of the foremost researchers in this area of digital design, this authoritative text provides in-depth theory and practical design solutions for the reliable working of synchronization and arbitration hardware in digital systems. The book provides methods for making real reliability measurements both on and off chip, evaluating some of the common difficulties and detailing circuit solutions at both circuit and system levels. Synchronization and Arbitration in Digital Systems also presents: mathematical models used to estimate mean time between failures in digital systems; a summary of serial and parallel communication techniques for on-chip data transmission; explanations on how to design a wrapper for a locally synchronous cell, highlighting the issues associated with stoppable clocks; an examination of various types of priority arbiters, using signal transition graphs to show the specification of different designs (from the simplest to more complex multi-way arbiters) including ways of solving problems encountered in a wide range of applications; essential information on systems composed of independently timed regions, including a discussion on the problem of choice and the factors affecting the time taken to make choices in electronics. With its logical approach to design methodology, this will prove an invaluable guide for electronic and computer engineers and researchers working on the design of digital electronic hardware. Postgraduates and senior undergraduate students studying digital systems design as part of their electronic engineering course will struggle to find a resource that better details the information given inside this book
The title provides a comprehensive treatment of synchronization in packet-switched networks, a tutorial on clocks and timing metrics, and explores issues of real-time services in TDM and IP networks.
Synchronization is one of the important issues in digital system design. While other approaches have always been intriguing, up until now synchro nous operation using a common clock has been the dominant design philo sophy. However, we have reached the point, with advances in technology, where other options should be given serious consideration. This is because the clock periods are getting much smaller in relation to the interconnect propagation delays, even within a single chip and certainly at the board and backplane level. To a large extent, this problem can be overcome with care ful clock distribution in synchronous design, and tools for computer-aided design of clock distribution. However, this places global constraints on the design, making it necessary, for example, to redesign the clock distribution each time any part of the system is changed. In this book, some alternative approaches to synchronization in digital sys tem design are described and developed. We owe these techniques to a long history of effort in both digital system design and in digital communica tions, the latter field being relevant because large propagation delays have always been a dominant consideration in design. While synchronous design is discussed and contrasted to the other techniques in Chapter 6, the dom inant theme of this book is alternative approaches.
