Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process
Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process

Author: Quincy Kwan-Lun Fung

Publisher:

Published: 2008

Total Pages: 194

ISBN-13: 9780494397350

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This thesis describes the design and implementation of an 8 bit, 2 GSamples/s analog to digital converter for a 0.18 mum SiGe BiCMOS process with a unity gain cut off frequency of 60 GHz. This folding and interpolation ADC consists of a highly linear track-and-hold amplifier (THA) with 10 bit resolution, a differential resistor ladder, four folding amplifiers, an interpolation stage, a comparator array, a digital encoder with bubble error correction scheme and a coarse quantizer. The microchip area is 3.0 x 3.4 mm2 including pads and buffer circuits. Simulation results show that this ADC has a maximum signal-to-noise and distortion ratio (SNDR) of 48.9 dB corresponding to a 7.5 effective number of bits (ENOB) and an effective resolution bandwidth (ERBW) of 700MHz. The circuit demonstrates a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.4 and 0.8 LSB, respectively while consuming 3.1W from a single 3.5 V supply.

An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter
An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter

Author: Wei An

Publisher:

Published: 2000

Total Pages: 0

ISBN-13:

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This thesis deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional 0.5 [mu]m self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency fT of 25GHz. The high-speed and high-resolution A/D converter has applications in direct IF sampling receivers for wideband communications systems. The folding-interpolating architecture offers an optimum solution for Gsample/s, high-resolution A/D converters in terms of system complexity, power dissipation and chip area. The use of a silicon bipolar process allows the integration of Gsample/s ADCs with DSP systems usually realized by silicon CMOS or BiCMOS processes. The 8-bit, 1-Gsample/s A/D converter consists of a reference ladder; four folding blocks for the fine quantizer and one folding block for the coarse quantizer; interpolation resistive strings; a comparator array; a digital encoder including an EXOR array, an error-correction stage, and a 31-to-5 OR ROM; and a coarse quantizer. All circuit blocks are integrated on one chip. The chip area of the circuitry is 2.5mm x 3.5mm including bonding pads. The converter exhibits a better than 7-bit ENOB with an input signal frequency of 200MHz and at a sampling rate of 1-Gsample/s The maximum power dissipation of the ADC is 2.5W using a 5-V power supply.

Design of High Speed Folding and Interpolating Analog-to-digital Converter
Design of High Speed Folding and Interpolating Analog-to-digital Converter

Author: Yunchu Li

Publisher:

Published: 2004

Total Pages:

ISBN-13:

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High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F & I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F & I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F & I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35 ơm CMOS process to verify the ideas. The S/H and F & I ADC prototype is realized in 0.35 [mu]m double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.

Low-Power High-Resolution Analog to Digital Converters
Low-Power High-Resolution Analog to Digital Converters

Author: Amir Zjajo

Publisher: Springer

Published: 2011-08-17

Total Pages: 250

ISBN-13: 9789048197262

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With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.