Design and Test of High Performance Network-on-chip Architecture for Highly Integrated Systems
Author: Ming Li
Publisher:
Published: 2006
Total Pages: 116
ISBN-13:
DOWNLOAD EBOOKA layered architecture called Network-on-Chip (NoC) has been recently proposed for global communication in a complex System-on-Chip (SoC) design to meet the performance requirements, and many new design and testing issues come up correspondingly. In this work, we aim to develop an efficient test strategy for NoC embedded core testing with a high performance router architecture which can support normal mode as well as testing mode operations. For normal mode router design, we propose to use a novel dynamic XY (namely DyXY) routing method, which provides adaptive routing based on congestion conditions in the proximity, and ensures deadlock-free and livelock-free features at the same time. Analytical models based on queuing theory are developed for DyXY routing in two-dimensional mesh architectures, and analytical results match very much with the simulation results. It is observed that DyXY routing can achieve much better performance when compared with static XY routing and odd-even routing. Hardware is also designed to support the DyXY routing method efficiently. For embedded core testing, we propose a multiple-data-flit-format (MDFF) test data transportation concept, a heuristic wrapper scan chain configuration method, and a test scheduling algorithm which considers both channel capacity and flit interleaving in the channels and routers. By applying the proposed test scheduling method together with the MDFF concept and the heuristic scan chain configuration method, the on-chip network channel of a NoC can be fully utilized for embedded core testing, the test time for the entire NoC can be minimized, and the test power dissipation can be controlled well. By comparing the results with other published works, it has been demonstrated that the proposed test scheduling method can achieve significant improvement on the test time for the entire NoC. To support the proposed embedded core testing strategy, design issues for testing mode operations have also been explored, and a complete router architecture is presented to support both normal mode (DyXY) and test mode operations. With all these works completed, we have an efficient NoC embedded core testing strategy with the support of a router architecture which provides high performances in test mode and normal mode operations.