Design and Evaluation of Efficient Router Architecture for Triplet-Based Network-on-Chip Topology
Design and Evaluation of Efficient Router Architecture for Triplet-Based Network-on-Chip Topology

Author: Yang Zhang

Publisher:

Published: 2014

Total Pages: 13

ISBN-13:

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A network-on-chip (NoC) router serves an important function in network communication performance. A high-performance router will help build a high-throughput, power-efficient, and low-latency NoC. However, the existing baseline router of a triplet-based NoC topology cannot fully optimize the potential performance, because it does not consider the characteristics of triplet-based NoC topology. This paper presents the topology-related router architecture for a triplet-based topology, called X Router. The baseline router architecture is optimized using four measures, namely, simplified crossbar switch, express virtual channel, group-priority scheme, and shared buffer organization. Simulation results using the cycle-accurate simulator Noxim show that the X Router cannot only decrease traffic latency and energy consumption, but also improve throughput over the baseline router architecture.

Design and Evaluation of High-throughput Network-on-chip Router Architecture
Design and Evaluation of High-throughput Network-on-chip Router Architecture

Author: Chifeng Wang

Publisher:

Published: 2012

Total Pages: 175

ISBN-13: 9781267248367

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Technology scaling has driven multi-core development inside a chip. On-chip interconnect implementation becomes one of the major challenges when considering large scale of VLSI designs. Although bus architecture has prevailed for the past decade, it no longer can fulfill the stringent application requirements for designs with hundreds of cores. Therefore Network-on-Chip (NoC) architecture is proposed as a unified solution to tackle interconnection design problems. This dissertation proposed two innovative NoC architectures, DMesh and WNoC, to improve transmission performance, energy dissipation and network throughput. DMesh deployed diagonal channels adopts a quasi-minimal adaptive routing algorithm to balance traffic load and prevent congestion for a two-dimensional mesh network. A low-cost scalable congestion-aware mechanism was devised to resolve load imbalance and increase traffic accommodation. Significant performance improvement can be observed from simulation results. To further augment resource utilization efficiency, QoS provision was equipped to support differentiated service for versatile applications. QoS-aware router design was realized and synthesized to estimate implementation overhead in terms of area and power consumption. Furthermore, power-aware design was achieved by introducing a statistical power model. Experimental results have shown that transfer latency and throughput are greatly improved and overall system power dissipation is also decreased by the insertion of diagonal links. As hundreds or thousands of cores are integrated inside a chip, long distance communication and energy dissipation become more critical issues for designing interconnection networks. A hybrid infrastructure which incorporates on-chip wireless interconnect along with existing wired NoC was proposed. Customized wireless link insertion algorithm was studied. Simulated annealing optimization technique was employed to decide placement for wireless routers in order to minimize transmission time. Congestion management utilizing both global and local network conditions to make routing decision was devised. Balanced traffic helped to prevent congestion situations and enhanced network bandwidth utilization. Performance evaluation and feasibility analysis have demonstrated the proposed approach as a promising solution to deal with wide ranges of communication tasks.

Microarchitecture of Network-on-Chip Routers
Microarchitecture of Network-on-Chip Routers

Author: Giorgos Dimitrakopoulos

Publisher: Springer

Published: 2014-08-27

Total Pages: 183

ISBN-13: 1461443016

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This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators’ structure and algorithms. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of NoC routers' architecture, the associated design challenges, and the available solutions.

Design and Development of Reliable and Fault-tolerant Network-on-chip Router Architecture
Design and Development of Reliable and Fault-tolerant Network-on-chip Router Architecture

Author: Abdulaziz Alhussien

Publisher:

Published: 2013

Total Pages: 137

ISBN-13: 9781303167805

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Networks on Chip (NoC) systems have been proposed as potential solutions for the interconnect demands in multi-processor System-on-Chip (MPSoC) environments. With the increase in the number of transistors on-chip and as CMOS technology scales down to nano technology, electronic components and interconnects are vulnerable to the effects of radiation, temperature variations and fabrication defects. The reliability of interconnection networks becomes a critical design factor. This has led to the design and the development of robust and fault-tolerant architectures. This dissertation addresses some of the key challenges in designing fault-tolerant NoC systems. Fault-tolerant adaptive routing algorithms for 2D mesh NoC architectures are proposed. The new adaptive routing algorithms for NePA architecture are able to tolerate faults in links in the NoC by rerouting packets in a proper alternative direction. The required hardware and software extensions are discussed and the performance of the router design is evaluated. The performance and its hardware complexity of the router demonstrate the feasibility of providing fault-tolerance design for NoC. Moreover, deadlock and livelock situations affect the functionality and the performance of NoC platforms. Thus. this dissertation considers these challenges as well when developing routing algorithms. The routing algorithms are verified to provide low overhead performance while ensuring deadlock/livelock freedom. This dissertation also proposes fault-tolerant routing algorithms for high throughput Diagonal Mesh NePA (DMesh) NoC. The routing algorithms are optimized to achieve efficient performance and low cost overhead while maintaining the correctness and deadlock/livelock freedom. To achieve high performance computing, hundreds of cores are integrated inside a chip. As cores and interconnections run synchronously at certain frequencies, Electromagnetic Interference (EMI) becomes very high and may affect the electronic circuits and therefore generate faults. An asynchronous NoC chip that is based on delay-insistent logic is proposed. Performance evaluation has demonstrated the proposed approach as a solution to implement Globally Asynchronous/Locally synchronous (GALS) architectures.

A Fine-grained Modular Architecture for System-on-chip Networks
A Fine-grained Modular Architecture for System-on-chip Networks

Author: Jongman Kim

Publisher:

Published: 2006

Total Pages: 23

ISBN-13:

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Abstract: "Packet-based interconnection networks are increasingly adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Networks-on-Chip (NoC) are required to not only provide ultra-low latency, but also occupy a small footprint and consume as little energy as possible. Further, reliability is rapidly becoming a major challenge in deep sub-micron technologies due to the increased prominence of permanent faults resulting from accelerated aging effects and manufacturing/testing challenges. Towards the goal of designing low-latency, energy-efficient and reliable on-chip communication networks, we propose a novel fine-grained modular router architecture. The proposed architecture employs decoupled parallel arbiters and uses smaller crossbars for row and column connections to reduce output port contention probabilities as compared to existing designs. Furthermore, the router employs a new switch allocation technique known as 'Mirroring Effect' to reduce arbitration depth and increase concurrency. In addition, the modular design permits graceful degradation of the network in the event of permanent faults and also helps to reduce the dynamic power consumption. Our simulation results, performed using a cycle-accurate simulator and the synthesized implementation of the router design in 90nm CMOS technology, show that the proposed architecture reduces packet latency by 4-40% and power consumption by 6-20% as compared to two existing router architectures evaluated in this work. We also show that the proposed architecture is more resilient to faults and offers 7-70% improvement in packet completion probability for different fault patterns. Evaluation using a combined performance, energy and fault-tolerance metric indicates that the proposed architecture provides 35-50% overall improvement compared to the two earlier routers."

Efficient Microarchitecture for Network-on-chip Routers
Efficient Microarchitecture for Network-on-chip Routers

Author: Daniel Ulf Becker

Publisher:

Published: 2012

Total Pages:

ISBN-13:

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Continuing advances in semiconductor technology, coupled with an increasing concern for energy efficiency, have led to an industry-wide shift in focus towards modular designs that leverage parallelism in order to meet performance goals. Networks-on-Chip (NoCs) are widely regarded as a promising approach for addressing the communication challenges associated with future Chip Multi-Processors (CMPs) in the face of further increases in integration density. In the present thesis, we investigate implementation aspects and design trade-offs in the context of routers for NoC applications. In particular, our focus is on developing efficient control logic for high-performance router implementations. Using parameterized RTL implementations, we first evaluate representative Virtual Channel (VC) and switch allocator architectures in terms of matching quality, delay, area and power. We also investigate the sensitivity of these properties to key network parameters, as well as the impact of allocation on overall network performance. Based on the results of this study, we propose microarchitectural modifications that improve delay, area and energy efficiency: Sparse VC allocation reduces the complexity of VC allocators by exploiting restrictions on transitions between packet classes. Two improved schemes for speculative switch allocation improve delay and cost while maintaining the critical latency improvements at low to medium load; this is achieved by incurring a minimal loss in throughput near the saturation point. We also investigate a practical implementation of combined VC and switch allocation and its impact on network cost and performance. The second part of the thesis focuses on router input buffer management. We explore the design trade-offs involved in choosing a buffer organization, and we evaluate practical static and dynamic buffer management schemes and their impact on network performance and cost. We furthermore show that buffer sharing can lead to severe performance degradation in the presence of congestion. To address this problem, we introduce Adaptive Backpressure (ABP), a novel scheme that improves the utilization of dynamically managed router input buffers by varying the stiffness of the flow control feedback loop based on downstream congestion. By inhibiting unproductive buffer occupancy, this mitigates undesired interference effects between workloads with differing performance characteristics.

Energy-efficient NoC Router Design with Adaptive Fault-tolerance
Energy-efficient NoC Router Design with Adaptive Fault-tolerance

Author: Cheng Li

Publisher:

Published: 2017

Total Pages: 159

ISBN-13:

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"Energy-efficiency and fault-tolerance have become key challenges in the design of network-on-chip (NoC) using nanoscale technologies. As the communication backbone of chip multiprocessor (CMP), NoC consumes a significant portion of on-chip power which has already been one of the most critical constraints for chip design. Improving energy-efficiency of NoC thus becomes an imperative issue. On the other hand, due to the aggressive transistor scaling, on-chip defects increase at each new technology node. Unfortunately, NoC is susceptible to faults as NoC nodes highly depend on each other to establish a communication path. Failure of even one of these nodes can paralyze a large region of healthy cores that connected via it. Fault-tolerance thus becomes a great concern in NoC design. Current fault-tolerant NoC designs, however, either cannot provide enough protection from severe faults in the worst case or incur prohibitively high area, performance, and power overhead in the typical case. This thesis aims to improve energy-efficiency and fault-tolerance of NoC at low cost by introducing novel designs of NoC routers. This thesis starts with an eDRAM-based router buffer that improves router area and energy efficiency at the component level. As a key element that can greatly impact NoC performance, buffer accounts for a significant portion of router area and power. Instead of using traditional SRAM, we implement the router buffer with planar eDRAM to leverage its small size and low-power potential. We demonstrate that the retention time of currently available eDRAM is much higher than the requirement for NoC. The implementation overhead is reduced by adopting a lightweight sense amplifier and a need-based refresh mechanism accordingly. Our design significantly reduces buffer area and power while maintaining a similar performance as that of the SRAM-based buffer. Then a NoC router with a variable channel width is introduced to improve router energy efficiency at the architecture level. Based on the observation that short control messages account for a significant portion of NoC traffic, we use a wide channel to transmit long data messages while dynamically splitting it into two narrower channels for short messages and shutting down the unused channel to save energy. Experiment results show our proposed approach reduces NoC power consumption significantly under both real application traffic and synthetic traffic at negligible area overhead. To bridge the competing goals of energy efficiency and fault tolerance, we propose an energy-efficient NoC router that exhibits strong fault-tolerance by leveraging channel slicing. This router has three identical router slices connected via internal sharing paths. When faults occur in any of the slices, resource sharing is enabled to enhance fault-tolerance. Channel slicing reduces the overhead of applying power gating and improves energy efficiency. These router slices can also be harnessed for on-demand TMR, to improve fault-tolerance further and reduce the need for deploying costly onchip testers. With these techniques, our proposed router can tolerate more faults than the state-of-the-art fault-tolerant NoC routers and consumes significantly less energy."--Pages v-vii.

SCION: A Secure Internet Architecture
SCION: A Secure Internet Architecture

Author: Adrian Perrig

Publisher: Springer

Published: 2018-08-25

Total Pages: 0

ISBN-13: 9783319883748

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This book describes the essential components of the SCION secure Internet architecture, the first architecture designed foremost for strong security and high availability. Among its core features, SCION also provides route control, explicit trust information, multipath communication, scalable quality-of-service guarantees, and efficient forwarding. The book includes functional specifications of the network elements, communication protocols among these elements, data structures, and configuration files. In particular, the book offers a specification of a working prototype. The authors provide a comprehensive description of the main design features for achieving a secure Internet architecture. They facilitate the reader throughout, structuring the book so that the technical detail gradually increases, and supporting the text with a glossary, an index, a list of abbreviations, answers to frequently asked questions, and special highlighting for examples and for sections that explain important research, engineering, and deployment features. The book is suitable for researchers, practitioners, and graduate students who are interested in network security.

Networks on Chip
Networks on Chip

Author: Axel Jantsch

Publisher: Springer Science & Business Media

Published: 2007-05-08

Total Pages: 304

ISBN-13: 0306487276

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As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.