Manufacturable Process/Tool for High-k/Metal Gate
Manufacturable Process/Tool for High-k/Metal Gate

Author: Aarthi Venkateshan

Publisher: VDM Publishing

Published: 2008-11-01

Total Pages: 204

ISBN-13: 9783836481564

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Off state leakage current related power dominates the CMOS heat dissipation problem of state of the art silicon integrated circuits. In this study, this issue has been addressed in terms of a low-cost single wafer processing (SWP) technique using a single tool for the fabrication of high- dielectric gate stacks for sub-45 nm CMOS. A system for monolayer photoassisted deposition was modified to deposit high-quality HfO2 films with in-situ clean, in-situ oxide film deposition, and in-situ anneal capability. The system was automated with Labview 8.2 for gas/precursor delivery, substrate temperature and UV lamp. The gold-hafnium oxide-aluminum (Au-HfO2-Al) stacks processed in this system had superior quality oxide characteristics with gate leakage current density on the order of 1 x 10-12 A/cm2 @ 1V and maximum capacitance on the order of 75 nF for EOT=0.39 nm. Achieving low leakage current density along with high capacitance demonstrated the excellent performance of the process developed. Detailed study of the deposition characteristics such as linearity, saturation behavior, film thickness and temperature dependence was performed for tight control on process parameters. Using Box-Behnken design of experiments, process optimization was performed for an optimal recipe for HfO2 films. UV treatment with in-situ processing of metal/high- dielectric stacks was studied to provide reduced variation in gate leakage current and capacitance. High-resolution transmission electron microscopy (TEM) was performed to calculate the equivalent oxide thickness (EOT) and dielectric constant of the films. Overall, this study shows that the in-situ fabrication of MIS gate stacks allows for lower processingcosts, high throughput, and superior device performance.

Advanced Gate Stacks for High-Mobility Semiconductors
Advanced Gate Stacks for High-Mobility Semiconductors

Author: Athanasios Dimoulas

Publisher: Springer Science & Business Media

Published: 2008-01-01

Total Pages: 397

ISBN-13: 354071491X

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This book provides a comprehensive monograph on gate stacks in semiconductor technology. It covers the major latest developments and basics and will be useful as a reference work for researchers, engineers and graduate students alike. The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any closer to a viable Ge and III-V MOS technology.

Physics and Technology of High-k Gate Dielectrics 4
Physics and Technology of High-k Gate Dielectrics 4

Author: Samares Kar

Publisher: The Electrochemical Society

Published: 2006

Total Pages: 565

ISBN-13: 1566775035

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This issue covers, in detail, all aspects of the physics and the technology of high dielectric constant gate stacks, including high mobility substrates, high dielectric constant materials, processing, metals for gate electrodes, interfaces, physical, chemical, and electrical characterization, gate stack reliability, and DRAM and non-volatile memories.

Metal Alloys and Gate Stack Engineering for CMOS Gate Electrode Application
Metal Alloys and Gate Stack Engineering for CMOS Gate Electrode Application

Author:

Publisher:

Published: 2004

Total Pages:

ISBN-13:

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The purpose of this research has been to search for proper metallic gate electrodes for CMOS devices. This dissertation covers several binary alloy metal gate research topics. First, intermetallic binary alloy RuY was investigated. From C-V analysis we obtained the effective work function of Ru-Y thin films to range from 5.0eV to 3.9eV which is suitable for dual metal gate CMOS. The rich Y film was found to be not stable on SiO2 dielectrics because of the high oxygen affinity of Y. RuxYy thin film may still be a candidate for low temperature process, especially due to its large range of work function. More over, RuY has smaller grain size than Ru which demonstrates one of the advantages of alloy by reducing grain size to achieve more uniform gate film and more uniform effective work function for the nano-size device applications. Chapter 3 presents MoxTay as a potential candidate for dual metal CMOS applications. The electrical characterization results of MoTa alloy indicates that the effective work function can be controlled to around 4.3 eV on SiO2 and is suitable for NMOS gate electrode application. The MoTa alloy forms a solid solution instead of an intermetallic compound. We report that the MoTa solid solution can achieve low work function values and is stable up to 900 & deg;C. X-ray diffraction results indicated only a single MoTa alloy phase. Moreover, from Auger electron spectroscopy and Rutherford backscattering spectroscopy analysis, MoTa was found to be stable on SiO2 under high temperature anneals and no metal diffusion into substrate Si channel was detected. This indicates that MoxTay is a good candidate for CMOS metal gate applications. Chapter 4 evaluates Ru and W capping layer for MoTa metal gate electrodes in Metal Oxide Semiconductor capacitor applications. We report that the oxygen diffusion from the capping layer plays an important role in determining the MoTa alloy effective work function value on SiO2. MoTa alloy metal gate with Ru capping exhib.