This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains. A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis. Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.
This comprehensive resource provides the latest information on digitization and reconstruction (D&R) of analog signals in digital radios. Readers learn how to conduct comprehensive analysis, concisely describe the major signal processing procedures carried out in the radios, and demonstrate the dependence of these procedures on the quality of D&R. The book presents and analyzes the most promising and theoretically sound ways to improve the characteristics of D&R circuits and illustrate the influence of these improvements on the capabilities of digital radios. The book is intended to bridge the gap that exists between theorists and practical engineers developing D&R techniques by introducing new signal transmission and reception methods that can effectively utilize the unique capabilities offered by novel digitization and reconstruction techniques.
This book comprises select papers from the international conference on Research in Intelligent and Computing in Engineering (RICE 2019) held at Hanoi University of Industry, Hanoi, Vietnam. The volume focuses on current research on various computing models such as centralized, distributed, cluster, grid and cloud. The contents cover recent advances in wireless sensor networks, mobile ad hoc networks, internet of things, machine learning, grid and cloud computing, and their various applications. The book will help researchers as well as professionals to gain insight into the rapidly evolving fields of internet computing and data mining.
This book is a current, comprehensive design guide for your digital processing work with today's complex receiver systems. This book brings you up-to-date with the latest information on wideband electronic warfare receivers, the ADC testing procedure, frequency channelization and decoding schemes, and the operation of monobit receivers.
This book is based on my doctoral thesis at the Helsinki University of Technology. Several different projects during five years guided me from the basics of the RF IC design to the implementations of highly integrated radio receiver chips. Sharing time and effort between IC and system issues is not always straightforward. I have been lucky to follow both topics and share experiences with diligent and enthusiastic people having different specialities. As a result, this book will cover a wide range of different topics needed in the design of highly integrated radio receivers. Experiences from the first receiver prototypes for the third generation cellular systems form the basis of this book. Most of the issues are directly related to the early proposals of European and Japanese standardization organizations. For example, the chip rate was originally set to 4. 096 Mcps in a wide-band CDMA channel. I have kept that number in the book in most of the examples although it has been later changed to 3. 84 Mcps. I hope that the readers will accept that and the possible other incompabilities to the latest specifications. At least in the research phase the changes even in the most essential requirements are definitely not a rare incident and IC designers should be able to react and modify their designs as soon as they can.
Software defined radio (SDR) is one of the most important topics of research, and indeed development, in the area of mobile and personal communications. SDR is viewed as an enabler of global roaming and as a unique platform for the rapid introduction of new services into existing live networks. It therefore promises mobile communication networks a major increase in flexibility and capability. SDR brings together two key technologies of the last decade - digital radio and downloadable software. It encompasses not only reconfiguration of the air interface parameters of handset and basestation products but also the whole mobile network, to facilitate the dynamic introduction of new functionality and mass-customised applications to the user's terminal, post-purchase. This edited book, contributed by internationally respected researchers and industry practitioners, describes the current technological status of radio frequency design, data conversion, reconfigurable signal processing hardware, and software issues at all levels of the protocol stack and network. The book provides a holistic treatment of SDR addressing the full breadth of relevant technologies - radio frequency design, signal processing and software - at all levels. As such it provides a solid grounding for a new generation of wireless engineers for whom radio design in future will assume dynamic flexibility as a given. In particular it explores * The unique demands of SDR upon the RF subsystem and their implications for front end design methodologies * The recent concepts of the 'digital front end' and 'parametrization' * The role and key influence of data conversion technologies and devices within software radio, essential to robust product design * The evolution of signal processing technologies, describing new architectural approaches * Requirements and options for software download * Advances in 'soft' protocols and 'on-the-fly' software reconfiguration * Management of terminal reconfiguration and its network implications * The concepts of the waveform description language The book also includes coverage of * Potential breakthrough technologies, such as superconducting RSFQ technology and the possible future role of MEMS in RF circuitry * Competing approaches, eg all-software radios implemented on commodity computing vs advanced processing architectures that dynamically optimise their configuration to match the algorithm requirements at a point in time The book opens with an introductory chapter by Stephen Blust, Chair of the ITU-R WP8F Committee and Chair of the SDR Forum presenting a framework for SDR, in terms of definitions, evolutionary perspectives, introductory timescales and regulation. Suitable for today's engineers, technical staff and researchers within the wireless industry, the book will also appeal to marketing and commercial managers who need to understand the basics and potential of the technology for future product development. Its balance of industrial and academic contributors also makes it suitable as a text for graduate and post-graduate courses aiming to prepare the next generation of wireless engineers.
Today everything tends to be connected in the Internet of Things (IoT) universe, where a broad variety of communication standards and technologies are used for those connected devices. It is always a dream to design a Software-Defined Radio (SDR) supporting different standards solely based on the software configuration. As integrated-circuit (IC) manufacture and design advance, a partial of SDR can be realized. This thesis investigates one of the most important parts in a SDR: the analog design of a direct sampling (DS) receiver, which mainly consists of a broadband RF front end and a wideband ADC. Especially, a DS receiver shows a great flexibility and efficiency for the simultaneous reception of multiple channels comparing with the traditional parallelism of superheterodyne structure. The research contributions of this work include (1) demonstration and comparative analysis of two new architectures of broadband RFPGAs: voltage-mode: RFPGA-V and current-mode: RFPGA-I. RFPGA-V and RFPGA-I utilize an innovative interpolation method and current steering approach, respectively, to achieve a fine gain step of 0.25-dB over 40-dB gain range for several GHz frequency range. Besides, with innovative design, no off-chip inductor is needed for the both RFPGAs. (2) The design of a 5-GS/s 10b time-interleaved SAR. The ADC power efficiency is significantly improved by many design techniques: the low-energy CDAC switching scheme, optimized input common-mode voltage for comparator, optimal reduced radix-2 capacitor ratio for low-power reference buffers and higher conversion speed, etc. The lane-to-lane mismatches in a time-interleave ADC are minimized by using optimal floor plan and then are calibrated digitally. Three prototypes: the broadband RF front ends with RFPGA-V, the broadband RF front ends with RFPGA-I and a 5-GHz ADC, are fabricated to verify the proposed ideas in 28nm CMOS technology
Offering engineers a thorough examination of special, more advanced aspects of digital wideband receiver design, this practical book builds on fundamental resources on the topic, helping you gain a more comprehensive understanding of the subject. This in-depth volume presents a detailed look at a complete receiver design, including the encoder. Moreover, it discusses the detection of exotic signals and provides authoritative guidance on designing receivers used in electronic warfare. From frequency modulation and biphase shifting keys, to parameter encoders in electronic warfare receivers and the use of the simulation and probability density function to predict the false alarm parameter, this book focuses on critical topics and techniques that help you design digital wideband receivers for top performance. The authoritative reference is supported with over 310 illustrations and more than 180 equations.
Digital Techniques for Wideband Receivers is widely recognized as the definitive design guide on digital processing work with today's complex receiver systems. This third edition brings readers up-to-date with the latest information on wideband electronic warfare receivers, and includes new chapters on the detection of FM and BPSK radar signals, analog-to-information, time-reversal filter, monobit receivers with improved instantaneous dynamic range and it offers insights on building electronic warfare receivers. From fundamental concepts and procedures, to recent technology advances in digital receivers, readers get practical solutions to important wideband receiver problems. This book has been updated with many of the latest concepts to help users design receivers that are relevant for today's electronic warfare systems. It will be an ideal reference for defense digital signal processing engineers, in government and industry.
Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.
