Background Adaptive Cancellation of Switching Noise in Pipelined Analog-to-digital Converters
Background Adaptive Cancellation of Switching Noise in Pipelined Analog-to-digital Converters

Author: Nick Chia-Jui Chang

Publisher:

Published: 2011

Total Pages:

ISBN-13: 9781267238412

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Switching noise generated by digital circuits can degrade analog circuit performance in mixed-signal integrated circuits (ICs). In an analog-to-digital converter (ADC), one major source of switching noise is digital output buffers. Traditional methods for mitigating this problem mostly have been to try to isolate the digital noise to reduce coupling into sensitive nodes. This dissertation presents two fully digital and adaptive algorithms, which find and cancel errors due to switching noise coupling at the output of an ADC without noise sensors. To demonstrate the operation of this algorithm, a 12-bit, 40-MS/s pipelined ADC has been designed and fabricated in 0.18-um CMOS process. The system consists of an ADC with its own output buffers, and eight other independent digital output buffers (noise buffers), which can be programmed to produce four different kinds of switching noise. The switching noise cancellation (SNC) algorithms estimate noise parameters in the ADC and store them in lookup tables implemented as RAMs. If the outputs of a digital noise source are known, the use of RAM eliminates the need for analog noise sensors, and scaling in advanced technologies reduces the cost of integrated memory. At the ADC output, the effects of switching noise is digitally removed to recover the input samples. Measured results show that the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 64.9 dB without any of the noise buffers on. With the noise buffers on, the worst-case SNDR before and after SNC is 51.9 dB and 63.7 dB, respectively.

Harmonic Distortion Correction in Pipelined Analog to Digital Converters
Harmonic Distortion Correction in Pipelined Analog to Digital Converters

Author: Andrea Panigada

Publisher:

Published: 2009

Total Pages: 80

ISBN-13:

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Pipelined analog to digital converters are widely used in telecommunication systems and instrumentation systems, where wide bandwidth analog input signals need to be converted into medium to high resolution digital signals. A pipelined analog to digital converter is sensitive to distortion introduced by its residue amplifiers, because such distortion leaks into the digital output signal, thus affecting the converter resolution. To reduce distortion, high performance operational amplifiers are usually required in the first few pipeline stages, but this causes the power consumption, the area occupation and therefore the cost of the converter to increase. An alternative approach is to design low performance operational amplifiers to reduce area and power, and compensate for the distortion they introduce by calibrating the signal in the digital domain. This dissertation presents a new digital background calibration technique called Harmonic Distortion Correction, which allows the estimation and correction of the distortion introduced by residue amplifiers in pipelined analog to digital converters. Implemented in a prototype pipelined analog to digital converter together with another digital calibration technique known in literature as DAC Noise Cancellation, Harmonic Distortion Correction has been proven to facilitate low-voltage operation and to enable reductions in power consumption relative to comparable conventional state-of-the-art pipelined analog to digital converters. Chapter 1 provides a mathematical model for the analysis of the distortion introduced by residue amplifiers in pipelined analog to digital converters, outlines the theory behind the Harmonic Distortion Correction algorithm, and presents the behavioral model of an example pipelined analog to digital converter implementing such technique. Chapter 2 presents a pipelined analog to digital converter integrated circuit prototype implementing Harmonic Distortion Correction and DAC Noise Cancellation, describes the system level and circuit level design issues and solutions, and provides the prototype measurement results.

Blind Nonlinear Substrate Noise Cancellation in Algorithmic Analog-to-digital Converters
Blind Nonlinear Substrate Noise Cancellation in Algorithmic Analog-to-digital Converters

Author: Yuan Hui Li

Publisher:

Published: 2012

Total Pages:

ISBN-13: 9781267758125

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Typical System on Chip (SOC) designs consist of both digital circuits and analog circuits. Performance of analog circuits on designs is affected by the substrate noise generated by the digital circuit switching. Several methods have been proposed to reduce the effect of substrate noise on analog circuits. Recently a new method has been proposed to cancel substrate noise in the digital domain. This method is based on an adaptive maximum likelihood (ML) algorithm for estimating the unknown noise parameters and recover input signal samples. Analysis of the new method was performed for single step analog-to-digital converters (ADC). This thesis extends the proposed method on a more complicated algorithmic ADC. An adaptive ML algorithm is first derived under the assumption that the distribution of input signal is known. Then a nearly universal algorithm which does not require any knowledge of the input signal distribution is obtained. Both algorithms are simplified and their convergences are studied by the ODE method. A Gaussian input signal and a sum of three sinusoids are used in Matlab simulations to evaluate the performance of both algorithms. Estimations of noise parameters are done in all simulations. Simulations show that both algorithms can estimate the unknown noise parameters with small relative errors. Simulations also show that the universal algorithm improves ADC spurious free dynamic range (SFDR) by 10dB to 23dB when other ADC imperfections are ignored.

MicroCMOS Design
MicroCMOS Design

Author: Bang-Sup Song

Publisher: CRC Press

Published: 2017-12-19

Total Pages: 436

ISBN-13: 1351833898

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MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and transistor-level design aspects. They must understand abstract concepts associated with large components, such as analog-to-digital converters (ADCs) and phase-locked loops (PLLs). To help readers along, this book discusses topics including: Amplifier basics & design Operational amplifier (Opamp) Data converter basics Nyquist-rate data converters Oversampling data converters High-resolution data converters PLL basics Frequency synthesis and clock recovery Focused more on design than analysis, this reference avoids lengthy equations and instead helps readers acquire a more hands-on mastery of the subject based on the application of core design concepts. Offering the needed perspective on the various design techniques for data converter and PLL design, coverage starts with abstract concepts—including discussion of bipolar junction transistors (BJTs) and MOS transistors—and builds up to an examination of the larger systems derived from microCMOS design.

Stochastic Process Variation in Deep-Submicron CMOS
Stochastic Process Variation in Deep-Submicron CMOS

Author: Amir Zjajo

Publisher: Springer Science & Business Media

Published: 2013-11-19

Total Pages: 207

ISBN-13: 9400777817

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One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.

Pipelined Analog-to-digital Conversion Using Class-AB Amplifiers
Pipelined Analog-to-digital Conversion Using Class-AB Amplifiers

Author: Kyung Ryun Kim

Publisher: Stanford University

Published: 2010

Total Pages: 128

ISBN-13:

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In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.