A 1.8 GHz LC-Voltage Controlled Oscillator Using On-chip Inductors and Body Driven Varactors in CMOS 0.35 [mu]m Process
A 1.8 GHz LC-Voltage Controlled Oscillator Using On-chip Inductors and Body Driven Varactors in CMOS 0.35 [mu]m Process

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Publisher:

Published: 2004

Total Pages:

ISBN-13:

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In an era dominated by the highly demanding wireless communication system, there is a great need for developing small, cheap, and low power RF sub-systems. This demand has lead to significant research on completely integrated transceiver systems. One of the great challenges in an integrated transceiver system is the frequency synthesizer. Frequency synthesizers are usually implemented using a phase locked loop (PLL) and low frequency highly stable crystal oscillator. The spectral purity of a synthesized carrier signal depends on the kind of Voltage Controlled Oscillator (VCO) used. Hence successful implementation of a low phase noise, completely integrated VCO in standard CMOS process is a major step towards implementing a completely integrated transceiver. The best VCO architecture in terms of noise performance is LC-VCO. The aim of the current research is to design a completely integrated 1.8 GHz LC-VCO for a GSM or DCS-1800 receiver in standard CMOS 0.35 [mu]m technology. The major challenge in a completely integrated LC-VCO is to develop an fully integrated inductor. In this research various means of implementing an integrated inductor have been scrutinized and the best feasible among them the on-chip spiral inductor has been analyzed elaborately. The complete design cycle from describing the specification of an inductor to the final layout in Cadence has been described. Also a new symmetrical, highly balanced on-chip inductor has been used in the current design. Another important and the most critical challenge is to implement a very high tuning range, high Q-factor on-chip varactor in standard CMOS process. In this research a new body driven varactor, which is forced to operate in accumulation mode has been developed and analyzed elaborately. The tuning range specification for the design was chosen to be 200 MHz accounting for component tolerance. Various means of measuring phase noise has been elaborately analyzed. Also detailed study on improving the noise performance of the LC-VCO has been studied.

Design of High-Performance CMOS Voltage-Controlled Oscillators
Design of High-Performance CMOS Voltage-Controlled Oscillators

Author: Liang Dai

Publisher: Springer Science & Business Media

Published: 2012-12-06

Total Pages: 170

ISBN-13: 1461511453

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Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

Millimeter-Wave Voltage-Controlled Oscillators in 0.13-micrometer CMOS Technology
Millimeter-Wave Voltage-Controlled Oscillators in 0.13-micrometer CMOS Technology

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Publisher:

Published: 2006

Total Pages: 9

ISBN-13:

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This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 micrometer result in both good quality factor (>12) and Cmax/Cmin ratio (~3) in the 0.13-micrometer CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of --102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15 mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results in a smaller circuit area.

A Low Power Low Phase Noise Voltage Controlled Oscillator
A Low Power Low Phase Noise Voltage Controlled Oscillator

Author: Kriyang Shah

Publisher:

Published: 2009

Total Pages: 282

ISBN-13:

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The explosive growth in wireless communication has driven research into low-cost, low-power and miniaturised wireless receivers. A low power and low phase noise voltage controlled oscillator (VCO) is one of the key components of transceiver systems. Close-in phase noise, responsible for jitter in time domain, is the most important parameter of a VCO as it results in inter-symbol interferences in high speed analogue to digital converters (ADCs). VCO phase noise also degrades system sensitivity and selectivity of wireless receivers. To improve battery life, VCO designs for wireless receivers must consume the least possible power. Hence, the primary aims of this research are to achieve a VCO with very low close-in phase noise and with low power consumption. Substantial research into VCO topologies and the design of on-chip passive elements has made on-chip complementary metal oxide semiconductor (CMOS) implementation of LC-tank VCO possible. However, the principle issues with CMOS LC-VCOs have been the unavailability of a high quality factor (Q) on-chip inductor and high flicker noise of active devices.

Mixed Analog-digital VLSI Devices and Technology
Mixed Analog-digital VLSI Devices and Technology

Author: Yannis Tsividis

Publisher: World Scientific

Published: 2002

Total Pages: 300

ISBN-13: 9789812381118

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Improve your circuit-design potential with this expert guide to the devices and technology used in mixed analog-digital VLSI chips for such high-volume applications as hard-disk drives, wireless telephones, and consumer electronics. The book provides you with a critical understanding of device models, fabrication technology, and layout as they apply to mixed analog-digital circuits.You will learn about the many device-modeling requirements for analog work, as well as the pitfalls in models used today for computer simulators such as Spice. Also included is information on fabrication technologies developed specifically for mixed-signal VLSI chips, plus guidance on the layout of mixed analog-digital chips for a high degree of analog-device matching and minimum digital-to-analog interference.This reference book features an intuitive introduction to MOSFET operation that will enable you to view with insight any MOSFET model ? besides thorough discussions on valuable large-signal and small-signal models.Filled with practical information, this first-of-its-kind book will help you grasp the nuances of mixed-signal VLSI-device models and layout that are crucial to the design of high-performance chips.