This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012. System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.
With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip (SoC) has become an essential technique to reduce product cost. With this progress and continuous reduction of feature sizes, and the development of very large-scale integration (VLSI) circuits, addressing the harder problems requires fundamental understanding
This book, the Mixed-signal Methodology Guide: Advanced Methodology for AMS IP and SoC Design, Verification, and Implementation provides a broad overview of the design, verification and implementation methodologies required for today's mixed-signal designs. The book covers mixed-signal design trends and challenges, abstraction of analog using behavioral models, assertion-based metric-driven verification methodology applied on analog and mixed-signal and verification of low power intent in mixed-signal design. It also describes methodology for physical implementation in context of concurrent mixed-signal design and for handling advanced node physical effects. The book contains many practical examples of models and techniques. The authors believe it should serve as a reference to many analog, digital and mixed-signal designers, verification, physical implementation engineers and managers in their pursuit of information for a better methodology required to address the challenges of modern mixed-signal design.
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. - Learn formal verification algorithms to gain full coverage without exhaustive simulation - Understand formal verification tools and how they differ from simulation tools - Create instant test benches to gain insight into how models work and find initial bugs - Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems
This book contains extended and revised versions of the best papers presented at the 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, held in Salt Lake City, UT, USA, in October 2020.* The 16 full papers included in this volume were carefully reviewed and selected from the 38 papers (out of 74 submissions) presented at the conference. The papers discuss the latest academic and industrial results and developments as well as future trends in the field of System-on-Chip (SoC) design, considering the challenges of nano-scale, state-of-the-art and emerging manufacturing technologies. In particular they address cutting-edge research fields like low-power design of RF, analog and mixed-signal circuits, EDA tools for the synthesis and verification of heterogenous SoCs, accelerators for cryptography and deep learning and on-chip Interconnection system, reliability and testing, and integration of 3D-ICs. *The conference was held virtually.
Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin's approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices. Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more. - Demonstrates a top-down approach to digital VLSI design. - Provides a systematic overview of architecture optimization techniques. - Features a chapter on field-programmable logic devices, their technologies and architectures. - Includes checklists, hints, and warnings for various design situations. - Emphasizes design flows that do not overlook important action items and which include alternative options when planning the development of microelectronic circuits.
This book constitutes the refereed proceedings of the ACM/IFIP/USENIX 12th International Middleware Conference, held in Lisbon, Portugal, in December 2011. The 22 revised full papers presented together with 2 industry papers and an invited paper were carefully reviewed and selected from 125 submissions. The papers are organized in topical sections on social networks, storage and performance management, green computing and resource management, notification and streaming, replication and caching, security and interoperability, and run-time (re)configuration and inspection.
This book brings together a selection of the best papers from the sixteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2013 in Paris, France. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems and mixed-technology systems.