The issues addressed by the Sixth International Symposium on the Ultra Clean Processing of Silicon Surfaces included all aspects of ultra-clean Si-technology, cleaning and contamination control in both front-end-of-line (FEOL) and back-end-of-line (BEOL) processing. Volume is indexed by Thomson Reuters CPCI-S (WoS). This covered studies of Si-surface chemistry and topography and its relationship to device performance and process yield, cleaning in relationship to new gate stacks, cleaning at the interconnect level, resist stripping and polymer removal, cleaning and contamination control of various new materials, wafer backside cleaning and cleaning following Chemical-Mechanical-Polishing (CMP).
The issues addressed by the Sixth International Symposium on the Ultra Clean Processing of Silicon Surfaces included all aspects of ultra-clean Si-technology, cleaning and contamination control in both front-end-of-line (FEOL) and back-end-of-line (BEOL) processing. This covered studies of Si-surface chemistry and topography and its relationship to device performance and process yield, cleaning in relationship to new gate stacks, cleaning at the interconnect level, resist stripping and polymer removal, cleaning and contamination control of various new materials, wafer backside cleaning and cleaning following Chemical-Mechanical-Polishing (CMP). Judging from the large number of papers dealing with wet cleaning processes, it is clear that this is still the dominant cleaning technology at the moment. Various papers discussed simplified cleaning by the use of chelating additives, and single-wafer wet cleaning; which is expected to replace the more standard multi-step batch-type cleaning systems, in various applications, in the future. Several contributions dealt with new materials introduced into current process research and development: such as Cu, and especially (porous) low-k material, as well as high-k and metal gate stacks. Substantial progress had also been made in understanding the effects of megasonics, and in the area of cleaning following Chemical-Mechanical Polishing (CMP). Last, but not least, an encouraging number of contributions were presented on the relatively new topic of supercritical CO2 cleaning. Altogether, the 76 contributions presented at the symposium represent a timely and authoritative assessment of the state-of-the-art of this very interesting and essential field.
Volume is indexed by Thomson Reuters CPCI-S (WoS). The proceedings of the Fifth International Symposium on Ultra Clean Processing of Silicon Surfaces cover all aspects of ultra-clean Si-technology: cleaning, contamination control, Si-surface chemistry and topography, and its relationship to device performance and process yield. New areas of concern include: cleaning at the interconnect level, resist strip and polymer removal (dry and wet), cleaning and contamination aspects of metallization, wafer backside cleaning and cleaning after Chemical-Mechanical-Polishing (CMP).
Volume is indexed by Thomson Reuters CPCI-S (WoS). This book is sub-divided into 10 different topical sections; each dealing with important issues in surface cleaning and preparation.
The proceedings of the Fourth International Symposium on Ultra Clean Processing of Silicon Surfaces (UCPSS '98) cover all aspects of ultra-clean Si-technology: cleaning, contamination control, Si-surface chemistry and topography, and its relationship to device performance and process yield. New areas of concern include: cleaning at the interconnect level, resist strip and polymer removal (dry and wet), cleaning and contamination aspects of metallization, wafer backside cleaning and cleaning after Chemical-Mechanical-Polishing (CMP).
Volume is indexed by Thomson Reuters CPCI-S (WoS). This collection of 86 peer-reviewed papers covers all aspects of the use of ultra-clean technology for large-scale integration on semiconductors, and cleaning and contamination-control in both front-end-of-line (FEOL) and back-end-of-line (BEOL) processing.
The proceedings of the Fifth International Symposium on Ultra Clean Processing of Silicon Surfaces cover all aspects of ultra-clean Si-technology: cleaning, contamination control, Si-surface chemistry and topography, and its relationship to device performance and process yield. New areas of concern include: cleaning at the interconnect level, resist strip and polymer removal (dry and wet), cleaning and contamination aspects of metallization, wafer backside cleaning and cleaning after Chemical-Mechanical-Polishing (CMP).
