IEEE Standard for SystemVerilog--unified Hardware Design, Specification, and Verification Language
IEEE Standard for SystemVerilog--unified Hardware Design, Specification, and Verification Language

Author: IEEE Computer Society. Design Automation Standards Committee

Publisher:

Published: 2013

Total Pages: 1275

ISBN-13: 9780738181103

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Abstract: The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, IEEE 1800, PLI, programming language interface, SystemVerilog, Verilog, VPI.