Cache and Interconnect Architectures in Multiprocessors
Cache and Interconnect Architectures in Multiprocessors

Author: Michel Dubois

Publisher: Springer Science & Business Media

Published: 2012-12-06

Total Pages: 286

ISBN-13: 1461315379

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Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.

Computer Architecture
Computer Architecture

Author: John L. Hennessy

Publisher: Morgan Kaufmann

Published: 2017-11-23

Total Pages: 939

ISBN-13: 0128119063

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Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major technical importance to the computing field, is fully revised with the latest developments in processor and system architecture. The text now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google's newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design. - Winner of a 2019 Textbook Excellence Award (Texty) from the Textbook and Academic Authors Association - Includes a new chapter on domain-specific architectures, explaining how they are the only path forward for improved performance and energy efficiency given the end of Moore's Law and Dennard scaling - Features the first publication of several DSAs from industry - Features extensive updates to the chapter on warehouse-scale computing, with the first public information on the newest Google WSC - Offers updates to other chapters including new material dealing with the use of stacked DRAM; data on the performance of new NVIDIA Pascal GPU vs. new AVX-512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization - Includes "Putting It All Together" sections near the end of every chapter, providing real-world technology examples that demonstrate the principles covered in each chapter - Includes review appendices in the printed text and additional reference appendices available online - Includes updated and improved case studies and exercises - ACM named John L. Hennessy and David A. Patterson, recipients of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry

An Analysis of the Interactions of Overhead-reducing Techniques for Shared-memory Multiprocessors
An Analysis of the Interactions of Overhead-reducing Techniques for Shared-memory Multiprocessors

Author: University of Wisconsin--Madison. Computer Sciences Dept

Publisher:

Published: 1995

Total Pages: 13

ISBN-13:

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Abstract: "The fine-grain nature of shared-memory multiprocessor communication introduces overheads that can be substantial. Using the Scalable Coherent Interface (SCI) as a base hardware platform and the SPLASH benchmark suite for applications, we analyze three techniques to reduce this overhead: (i) efficient synchronization primitives, and in particular a hardware primitive called QOLB; (ii) weakened memory ordering constraints; and (iii) optimization of the cache-coherence protocol for two nodes sharing data. We perform simulations both for current technology and technology that we anticipate will be available five years hence. We find that QOLB (of which this study performs the first detailed simulations) shows a large and consistent improvement, much larger than that predicted by Mellor-Crummey and Scott [19]. The relaxation of memory ordering constraints also provides a consistent performance improvement. In accordance with prior results, we show that a more aggressive memory model produces more substantial performance improvements. The optimization for two-node sharing shows mixed results, correlating unsurprisingly with the presence of that sharing pattern in an application. Our most important results are (i) that the overheads eliminated with these optimizations are largely orthogonal -- the performance gains from supporting multiple optimizations concurrently are for the most part additive -- and (ii) that technological improvements increase both these overheads and the success of the optimizations at reducing them."

Proceedings of the 1993 International Conference on Parallel Processing
Proceedings of the 1993 International Conference on Parallel Processing

Author: C.Y. Roger Chen

Publisher: CRC Press

Published: 1993-08-16

Total Pages: 392

ISBN-13: 9780849389849

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This three-volume work presents a compendium of current and seminal papers on parallel/distributed processing offered at the 22nd International Conference on Parallel Processing, held August 16-20, 1993 in Chicago, Illinois. Topics include processor architectures; mapping algorithms to parallel systems, performance evaluations; fault diagnosis, recovery, and tolerance; cube networks; portable software; synchronization; compilers; hypercube computing; and image processing and graphics. Computer professionals in parallel processing, distributed systems, and software engineering will find this book essential to their complete computer reference library.

The Cache Coherence Problem in Shared-Memory Multiprocessors
The Cache Coherence Problem in Shared-Memory Multiprocessors

Author: Igor Tartalja

Publisher: Wiley-IEEE Computer Society Press

Published: 1996-02-13

Total Pages: 368

ISBN-13:

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The book illustrates state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a brief overview of the cache coherence problem and introduces software solutions to the problem. The text defines and details static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies.