This volume on computational intelligence covers the 17th Conference on Advanced Research in VLSI in 1997. Topics include: VLSI architecture; asynchronous design; circuits; layout; image sensors; optimization; system timing; CAD; and low-power design.
How do we design a self-organizing system? Is it possible to validate and control non-deterministic dynamics? What is the right balance between the emergent patterns that bring robustness, adaptability and scalability, and the traditional need for verification and validation of the outcomes? The last several decades have seen much progress from original ideas of “emergent functionality” and “design for emergence”, to sophisticated mathematical formalisms of “guided self-organization”. And yet the main challenge remains, attracting the best scientific and engineering expertise to this elusive problem. This book presents state-of-the-practice of successfully engineered self-organizing systems, and examines ways to balance design and self-organization in the context of applications. As demonstrated in this second edition of Advances in Applied Self-Organizing Systems, finding this balance helps to deal with practical challenges as diverse as navigation of microscopic robots within blood vessels, self-monitoring aerospace vehicles, collective and modular robotics adapted for autonomous reconnaissance and surveillance, self-managing grids and multiprocessor scheduling, data visualization and self-modifying digital and analog circuitry, intrusion detection in computer networks, reconstruction of hydro-physical fields, traffic management, immunocomputing and nature-inspired computation. Many algorithms proposed and discussed in this volume are biologically inspired, and the reader will also gain an insight into cellular automata, genetic algorithms, artificial immune systems, snake-like locomotion, ant foraging, birds flocking, neuromorphic circuits, amongst others. Demonstrating the practical relevance and applicability of self-organization, Advances in Applied Self-Organizing Systems will be an invaluable tool for advanced students and researchers in a wide range of fields.
This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.
Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic. The only book to be entirely devoted to clocking Clocking has become one of the most important topics in the field of digital system design A "must have" book for advanced circuit engineers
The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.
The annual conference on Neural Information Processing Systems (NIPS) is the flagship conference on neural computation. It draws preeminent academic researchers from around the world and is widely considered to be a showcase conference for new developments in network algorithms and architectures. The broad range of interdisciplinary research areas represented includes computer science, neuroscience, statistics, physics, cognitive science, and many branches of engineering, including signal processing and control theory. Only about 30 percent of the papers submitted are accepted for presentation at NIPS, so the quality is exceptionally high. These proceedings contain all of the papers that were presented.