Reactive Ion Etching of Indium Phosphide-based Heterostructures and Field-effect Transistors Using Hydrogen Bromide Plasma
Reactive Ion Etching of Indium Phosphide-based Heterostructures and Field-effect Transistors Using Hydrogen Bromide Plasma

Author: Sambhulal Agarwala

Publisher:

Published: 1994

Total Pages:

ISBN-13:

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A new highly selective reactive ion etching process based on HBr plasma for the removal of InGaAs over InAlAs has been developed and the results are presented. The etch selectivity at a self-bias voltage of $-$100 V is over 160, which is the highest that has been reported for this material system so far. High etch selectivity is maintained over a wide range of chamber pressure and plasma self-bias voltages. The mechanism of this etch selectivity is determined to be due to the formation of involatile Al$sb2$O$sb3$. Selective HBr etching has been applied as the gate-recess process in the fabrication of InAlAs/InGaAs heterostructure FETs. Since less RIE-induced damage was observed in delta-doped structures, delta-doping was employed in all InP-based HFETs. The dc and rf device parameters of a typical 0.75-$mu$m gate-length transistor compare favorably with those of a corresponding device gate-recessed with a selective wet-etching technique. An extrinsic current-gain cutoff frequency of 150 GHz is obtained for a typical 0.2 $mu$m gate-length HFET device that was fabricated using selective HBr gate recess process. RIE-induced damage is characterized extensively using a variety of techniques such as AES, XPS, and SIMS analyses, Raman scattering, Hall measurements and Schottky characteristics. No significant degradation in surface properties is observed. The lattice damage in layer structures with 2DEG depth of greater than 20 nm was minimal. It is also observed that with increasing self-bias voltage the rate of removal of InGaAs increases faster than the rate of introduction of damage. An exponential distribution of damage with 1/e penetration depth of about 7.8 nm has been obtained. The exponential distribution of defects suggests that either ion channeling or diffusion is the possible mechanism of defect production in regions deeper than the projected range.

Plasma Etching Processes for CMOS Devices Realization
Plasma Etching Processes for CMOS Devices Realization

Author: Nicolas Posseme

Publisher: Elsevier

Published: 2017-01-25

Total Pages: 138

ISBN-13: 0081011962

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Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch compensation helps to create devices that are smaller than 20 nm. But, with the constant downscaling in device dimensions and the emergence of complex 3D structures (like FinFet, Nanowire and stacked nanowire at longer term) and sub 20 nm devices, plasma etching requirements have become more and more stringent. Now more than ever, plasma etch technology is used to push the limits of semiconductor device fabrication into the nanoelectronics age. This will require improvement in plasma technology (plasma sources, chamber design, etc.), new chemistries (etch gases, flows, interactions with substrates, etc.) as well as a compatibility with new patterning techniques such as multiple patterning, EUV lithography, Direct Self Assembly, ebeam lithography or nanoimprint lithography. This book presents these etch challenges and associated solutions encountered throughout the years for transistor realization. Helps readers discover the master technology used to pattern complex structures involving various materials Explores the capabilities of cold plasmas to generate well controlled etched profiles and high etch selectivities between materials Teaches users how etch compensation helps to create devices that are smaller than 20 nm

Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE): Nanofabrication Tool for High Resolution Pattern Transfer
Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE): Nanofabrication Tool for High Resolution Pattern Transfer

Author:

Publisher:

Published: 2001

Total Pages: 0

ISBN-13:

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High resolution lithography and directional ion etching are increasingly important for the fabrication of nanostructures. As part of this equipment proposal, a reactive ion etching system was purchased from Oxford Instruments for $305,000. The Army Research Office provided $274,000, and Caltech cost share amounted to $31,500. This instrument was connected and etching conditions were optimized for the fabrication of nanostructures in silicon, silicon dioxide and gallium arsenide. In this final progress report, we will present some examples of functional devices which have been defined by using this very capable ion etching system.

Design, Fabrication, and Characterization of a Compact Deep Reactive Ion Etching System for MEMS Processing
Design, Fabrication, and Characterization of a Compact Deep Reactive Ion Etching System for MEMS Processing

Author: Parker Andrew Gould

Publisher:

Published: 2014

Total Pages: 126

ISBN-13:

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A general rule of thumb for new semiconductor fabrication facilities (Fabs) is that revenues from the first year of production must match the capital cost of building the fab itself. With modem Fabs routinely exceeding $1 billion to build, this rule serves as a significant barrier to entry for groups seeking to commercialize new semiconductor devices aimed at smaller market segments which require a dedicated process. To eliminate this cost barrier we are working to create a small-scale production suite of tools that will processes small (~1") substrates and cost less than $1 million. By shrinking the size of the substrate, substantial savings can be realized in material usage, energy consumption, and, most importantly, capital costs. In this thesis, we present the development of the first tool in this suite of small substrate processing equipment, a deep reactive ion etcher (DRIE). DRIE tools are used to create highly anisotropic, high aspect-ratio trenches in silicon-a crucial element in the production of many microelectromechanical systems (MEMS) devices. We are targeting the Bosch Process method of DRIE, which is a time multiplexed process that rapidly alternates between an SF6-based reactive ion etching (RIE) step that isotropically etches silicon and a C4F8-based plasma-enhanced chemical vapor deposition (PECVD) step that passivates the sidewalls of the etched features. The rapid alternation between the RIE and PECVD steps allows highly anisotropic features to be etched in silicon. The DRIE system developed in this thesis is roughly the size of a microwave oven and costs just a fraction of commercial etching systems. The test results presented herein characterize the stability and operating limits of the vacuum and plasma generation systems, and demonstrate the system's raw etching capability using a mix of SF6 and O2 process gases. Etch rates exceeding 4 [mu]m/min with control of the etched profile are reported, with models fitted to the data indicating increased capabilities with optimized process conditions.