The International Conference on Application Specific Array Processors (ASAP 91) was held September 1991, in Barcelona, Spain. Application- specific computing may be the solution to many computationally intensive problems. Coverage here includes design, mapping techniques, synthesis and verification, and systolic array designs and design methodologies. No index. Annotation copyrighted by Book News, Inc., Portland, OR.
Papers presented at ASAP-94, held in August 1994. The conference serves as a forum for researchers from universities as well as industry who are interested in the fundamental aspects of application specific computing systems. Sessions are devoted to signal & image processing, CAD, case studies, meth
Papers, invited talks, and poster sessions from the July 1995 conference address problems and solutions in the field of parallel array algorithms and architectures for special-purpose systems. Topics include scheduling and mapping techniques, design methodologies, array architectures, computer arith
Application Specific Processors is written for use by engineers who are developing specialized systems (application specific systems). Traditionally, most high performance signal processors have been realized with application specific processors. The explanation is that application specific processors can be tailored to exactly match the (usually very demanding) application requirements. The result is that no `processing power' is wasted for unnecessary capabilities and maximum performance is achieved. A disadvantage is that such processors have been expensive to design since each is a unique design that is customized to the specific application. In the last decade, computer-aided design systems have been developed to facilitate the development of application specific integrated circuits. The success of such ASIC CAD systems suggests that it should be possible to streamline the process of application specific processor design. Application Specific Processors consists of eight chapters which provide a mixture of techniques and examples that relate to application specific processing. The inclusion of techniques is expected to suggest additional research and to assist those who are faced with the requirement to implement efficient application specific processors. The examples illustrate the application of the concepts and demonstrate the efficiency that can be achieved via application specific processors. The chapters were written by members and former members of the application specific processing group at the University of Texas at Austin. The first five chapters relate to specific arithmetic which often is the key to achieving high performance in application specific processors. The next two chapters focus on signal processing systems, and the final chapter examines the interconnection of possibly disparate elements to create systems.
This set of technical books contains all the information presented at the 1995 International Conference on Parallel Processing. This conference, held August 14 - 18, featured over 100 lectures from more than 300 contributors, and included three panel sessions and three keynote addresses. The international authorship includes experts from around the globe, from Texas to Tokyo, from Leiden to London. Compiled by faculty at the University of Illinois and sponsored by Penn State University, these Proceedings are a comprehensive look at all that's new in the field of parallel processing.
This three-volume work presents a compendium of current and seminal papers on parallel/distributed processing offered at the 22nd International Conference on Parallel Processing, held August 16-20, 1993 in Chicago, Illinois. Topics include processor architectures; mapping algorithms to parallel systems, performance evaluations; fault diagnosis, recovery, and tolerance; cube networks; portable software; synchronization; compilers; hypercube computing; and image processing and graphics. Computer professionals in parallel processing, distributed systems, and software engineering will find this book essential to complete their computer reference library.
Focal-plane sensor-processor imager devices are sensor arrays and processor arrays embedded in each other on the same silicon chip. This close coupling enables ultra-fast processing even on tiny, low power devices, because the slow and energetically expensive transfer of the large amount of sensory data is eliminated. This technology also makes it possible to produce locally adaptive sensor arrays, which can (similarly to the human retina) adapt to the large dynamics of the illumination in a single scene This book focuses on the implementation and application of state-of-the-art vision chips. It provides an overview of focal plane chip technology, smart imagers and cellular wave computers, along with numerous examples of current vision chips, 3D sensor-processor arrays and their applications. Coverage includes not only the technology behind the devices, but also their near- and mid-term research trends.
Techniques for Optimizing Multiprocessor Implementations of Signal Processing Applications An indispensable component of the information age, signal processing is embedded in a variety of consumer devices, including cell phones and digital television, as well as in communication infrastructure, such as media servers and cellular base stations. Multiple programmable processors, along with custom hardware running in parallel, are needed to achieve the computation throughput required of such applications. Reviews important research in key areas related to the multiprocessor implementation of multimedia systems Embedded Multiprocessors: Scheduling and Synchronization, Second Edition presents architectures and design methodologies for parallel systems in embedded digital signal processing (DSP) applications. It discusses application modeling techniques for multimedia systems, the incorporation of interprocessor communication costs into multiprocessor scheduling decisions, and a modeling methodology (the synchronization graph) for multiprocessor system performance analysis. The book also applies the synchronization graph model to develop hardware and software optimizations that can significantly reduce the interprocessor communication overhead of a given schedule. Chronicles recent activity dealing with single-chip multiprocessors and dataflow models This edition updates the background material on existing embedded multiprocessors, including single-chip multiprocessors. It also summarizes the new research on dataflow models for signal processing that has been carried out since the publication of the first edition. Harness the power of multiprocessors This book explores the optimization of interprocessor communication and synchronization in embedded multiprocessor systems. It shows you how to design multiprocessor computer systems that are streamlined for multimedia applications.
