Reviewing the various IC packaging, assembly, and interconnection technologies, this professional reference provides an overview of the materials and the processes, as well as the trends and available options that encompass electronic manufacturing. It covers both the technical issues and touches on some of the reliability concerns with the various technologies applicable to packaging and assembly of the IC. The book discusses the various packaging approaches, assembly options, and essential manufacturing technologies, among other relevant topics.
MICROELECTRONIC INTERCONNECTIONS AND MICROASSEMBL Y WORKSHOP 18-21 May 1996, Prague, Czech Republic Conference Organizers: George Harman, NIST (USA) and Pavel Mach (Czech Republic) Summary of the Technical Program Thirty two presentations were given in eight technical sessions at the Workshop. A list of these sessions and their chairpersons is attached below. The Workshop was devoted to the technical aspects of advanced interconnections and microassembly, but also included papers on the education issues required to prepare students to work in these areas. In addition to new technical developments, several papers presented overviews predicting the future directions of these technologies. The basic issue is that electronic systems will continue to be miniaturized and at the same time performance must continue to improve. Various industry roadmaps were discussed as well as new smaller packaging and interconnection concepts. The newest chip packages are often based on the selection of an appropriate interconnection method. An example is the chip-scale package, which has horizontal (x-y) dimensions,;; 20% larger than the actual silicon chip itself. The chip is often flip-chip connected to a micro ball-grid-array, but direct chip attach was described also. Several papers described advances in the manufacture of such packages.
This book presents a systematic approach in performing reliability assessment of solder joints using Finite Element (FE) simulation. Essential requirements for FE modelling of an electronic package or a single reflowed solder joint subjected to reliability test conditions are elaborated. These cover assumptions considered for a simplified physical model, FE model geometry development, constitutive models for solder joints and aspects of FE model validation. Fundamentals of the mechanics of solder material are adequately reviewed in relation to FE formulations. Concept of damage is introduced along with deliberation of cohesive zone model and continuum damage model for simulation of solder/IMC interface and bulk solder joint failure, respectively. Applications of the deliberated methodology to selected problems in assessing reliability of solder joints are demonstrated. These industry-defined research-based problems include solder reflow cooling, temperature cycling and mechanical fatigue of a BGA package, JEDEC board-level drop test and mechanisms of solder joint fatigue. Emphasis is placed on accurate quantitative assessment of solder joint reliability through basic understanding of the mechanics of materials as interpreted from results of FE simulations. The FE simulation methodology is readily applicable to numerous other problems in mechanics of materials and structures.
LEARN ABOUT MICROSYSTEMS PACKAGING FROM THE GROUND UP Written by Rao Tummala, the field’s leading author, Fundamentals of Microsystems Packaging is the only book to cover the field from wafer to systems, including every major contributing technology. This rigorous and thorough introduction to electronic packaging technologies gives you a solid grounding in microelectronics, photonics, RF, packaging design, assembly, reliability, testing, and manufacturing and its relevance to both semiconductors and systems. You’ll find: *Full coverage of electrical, mechanical, chemical, and materials aspects of each technology *Easy-to-read schematics and block diagrams *Fundamental approaches to all system issues *Examples of all common configurations and technologies—wafer level packaging, single chip, multichip, RF, opto-electronic, microvia boards, thermal and others *Details on chip-to-board connections, sealing and encapsulation, and manufacturing processes *Basics of electrical and reliability testing
Electronics has become the largest industry, surpassing agriculture, auto, and heavy metal industries. It has become the industry of choice for a country to prosper, already having given rise to the phenomenal prosperity of Japan, Korea, Singapore, Hong Kong, and Ireland among others. At the current growth rate, total worldwide semiconductor sales will reach $300B by the year 2000. The key electronic technologies responsible for the growth of the industry include semiconductors, the packaging of semiconductors for systems use in auto, telecom, computer, consumer, aerospace, and medical industries, displays, magnetic, and optical storage as well as software and system technologies. There has been a paradigm shift, however, in these technologies, from mainframe and supercomputer applications at any cost, to consumer applications at approximately one-tenth the cost and size. Personal computers are a good example, going from $500IMIP when products were first introduced in 1981, to a projected $IIMIP within 10 years. Thin, light portable, user friendly and very low-cost are, therefore, the attributes of tomorrow's computing and communications systems. Electronic packaging is defined as interconnection, powering, cool ing, and protecting semiconductor chips for reliable systems. It is a key enabling technology achieving the requirements for reducing the size and cost at the system and product level.
Heterogeneous integration uses packaging technology to integrate dissimilar chips, LED, MEMS, VCSEL, etc. from different fabless houses and with different functions and wafer sizes into a single system or subsystem. How are these dissimilar chips and optical components supposed to talk to each other? The answer is redistribution layers (RDLs). This book addresses the fabrication of RDLs for heterogeneous integrations, and especially focuses on RDLs on: A) organic substrates, B) silicon substrates (through-silicon via (TSV)-interposers), C) silicon substrates (bridges), D) fan-out substrates, and E) ASIC, memory, LED, MEMS, and VCSEL systems. The book offers a valuable asset for researchers, engineers, and graduate students in the fields of semiconductor packaging, materials sciences, mechanical engineering, electronic engineering, telecommunications, networking, etc.
This thoroughly revised and updated three volume set continues to be the standard reference in the field, providing the latest in microelectronics design methods, modeling tools, simulation techniques, and manufacturing procedures. Unlike reference books that focus only on a few aspects of microelectronics packaging, these outstanding volumes discuss state-of-the-art packages that meet the power, cooling, protection, and interconnection requirements of increasingly dense and fast microcircuitry. Providing an excellent balance of theory and practical applications, this dynamic compilation features step-by-step examples and vital technical data, simplifying each phase of package design and production. In addition, the volumes contain over 2000 references, 900 figures, and 250 tables. Part I: Technology Drivers covers the driving force of microelectronics packaging - electrical, thermal, and reliability. It introduces the technology developer to aspects of manufacturing that must be considered during product development. Part II: Semiconductor Packaging discusses the interconnection of the IC chip to the first level of packaging and all first level packages. Electrical test, sealing, and encapsulation technologies are also covered in detail. Part III: Subsystem Packaging explores board level packaging as well as connectors, cables, and optical packaging.
This book offers a comprehensive reference guide for graduate students and professionals in both academia and industry, covering the fundamentals, architecture, processing details, and applications of 3D microelectronic packaging. It provides readers an in-depth understanding of the latest research and development findings regarding this key industry trend, including TSV, die processing, micro-bumps for LMI and MMI, direct bonding and advanced materials, as well as quality, reliability, fault isolation, and failure analysis for 3D microelectronic packages. Images, tables, and didactic schematics are used to illustrate and elaborate on the concepts discussed. Readers will gain a general grasp of 3D packaging, quality and reliability concerns, and common causes of failure, and will be introduced to developing areas and remaining gaps in 3D packaging that can help inspire future research and development.
