Materials, Technology and Reliability of Low-k Dielectrics and Copper Interconnects
Author: Ting Y. Tsui
Publisher:
Published: 2006
Total Pages: 498
ISBN-13:
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Author: Ting Y. Tsui
Publisher:
Published: 2006
Total Pages: 498
ISBN-13:
DOWNLOAD EBOOKAuthor: R. J. Carter
Publisher:
Published: 2004-09
Total Pages: 432
ISBN-13:
DOWNLOAD EBOOKThe scaling of device dimensions with a simultaneous increase in functional density has imposed tremendous challenges for materials, technology, integration and reliability of interconnects. To meet requirements of the ITRS roadmap, new materials are being introduced at a faster pace in all functions of multilevel interconnects. The issues addressed in this book cannot be dispelled as simply selecting a low-k material and integrating it into a copper damascene process. The intricacies of the back end for sub-100nm technology include novel processing of low-k materials, employing pore-sealing techniques and capping layers, introducing advanced dielectric and diffusion barriers, and developing novel integration schemes. This is in addition to concerns of performance, yield, and reliability appropriate to nanoscaled interconnects. Although many challenges continue to impede progress along the ITRS roadmap, the contributions in this book confront them head-on. It provides a scientific understanding of the issues and stimulate new approaches to advanced multilevel interconnects.
Author:
Publisher:
Published: 2004
Total Pages: 440
ISBN-13:
DOWNLOAD EBOOKAuthor: Tapan Gupta
Publisher: Springer Science & Business Media
Published: 2010-01-22
Total Pages: 433
ISBN-13: 1441900764
DOWNLOAD EBOOKSince overall circuit performance has depended primarily on transistor properties, previous efforts to enhance circuit and system speed were focused on transistors as well. During the last decade, however, the parasitic resistance, capacitance, and inductance associated with interconnections began to influence circuit performance and will be the primary factors in the evolution of nanoscale ULSI technology. Because metallic conductivity and resistance to electromigration of bulk copper (Cu) are better than aluminum, use of copper and low-k materials is now prevalent in the international microelectronics industry. As the feature size of the Cu-lines forming interconnects is scaled, resistivity of the lines increases. At the same time electromigration and stress-induced voids due to increased current density become significant reliability issues. Although copper/low-k technology has become fairly mature, there is no single book available on the promise and challenges of these next-generation technologies. In this book, a leader in the field describes advanced laser systems with lower radiation wavelengths, photolithography materials, and mathematical modeling approaches to address the challenges of Cu-interconnect technology.
Author: Materials Research Society. Meeting
Publisher:
Published: 2003
Total Pages: 544
ISBN-13:
DOWNLOAD EBOOKAuthor:
Publisher: The Electrochemical Society
Published: 2003
Total Pages: 364
ISBN-13: 9781566773799
DOWNLOAD EBOOKAuthor: Mikhail Baklanov
Publisher: John Wiley & Sons
Published: 2012-02-17
Total Pages: 616
ISBN-13: 1119966868
DOWNLOAD EBOOKFinding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance. Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses: Interconnect functions, characterisations, electrical properties and wiring requirements Low-k materials: fundamentals, advances and mechanical properties Conductive layers and barriers Integration and reliability including mechanical reliability, electromigration and electrical breakdown New approaches including 3D, optical, wireless interchip, and carbon-based interconnects Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.
Author: Paul S. Ho
Publisher: Springer Science & Business Media
Published: 2012-12-06
Total Pages: 323
ISBN-13: 3642559085
DOWNLOAD EBOOKLow dielectric constant materials are an important component of microelectronic devices. This comprehensive book covers the latest low-dielectric-constant (low-k) materials technology, thin film materials characterization, integration and reliability for back-end interconnects and packaging applications in microelectronics. Highly informative contributions from leading academic and industrial laboratories provide comprehensive information about materials technologies for
Author: Mikhail Baklanov
Publisher: John Wiley & Sons
Published: 2012-04-02
Total Pages: 616
ISBN-13: 0470662549
DOWNLOAD EBOOKFinding new materials for copper/low-k interconnects is critical to the continuing development of computer chips. While copper/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance. Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses: Interconnect functions, characterisations, electrical properties and wiring requirements Low-k materials: fundamentals, advances and mechanical properties Conductive layers and barriers Integration and reliability including mechanical reliability, electromigration and electrical breakdown New approaches including 3D, optical, wireless interchip, and carbon-based interconnects Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.
Author: Yosi Shacham-Diamand
Publisher: Springer Science & Business Media
Published: 2009-09-19
Total Pages: 545
ISBN-13: 0387958681
DOWNLOAD EBOOKIn Advanced ULSI interconnects – fundamentals and applications we bring a comprehensive description of copper-based interconnect technology for ultra-lar- scale integration (ULSI) technology for integrated circuit (IC) application. In- grated circuit technology is the base for all modern electronics systems. You can ?nd electronics systems today everywhere: from toys and home appliances to a- planes and space shuttles. Electronics systems form the hardware that together with software are the bases of the modern information society. The rapid growth and vast exploitation of modern electronics system create a strong demand for new and improved electronic circuits as demonstrated by the amazing progress in the ?eld of ULSI technology. This progress is well described by the famous “Moore’s law” which states, in its most general form, that all the metrics that describe integrated circuit performance (e. g. , speed, number of devices, chip area) improve expon- tially as a function of time. For example, the number of components per chip d- bles every 18 months and the critical dimension on a chip has shrunk by 50% every 2 years on average in the last 30 years. This rapid growth in integrated circuits te- nology results in highly complex integrated circuits with an increasing number of interconnects on chips and between the chip and its package. The complexity of the interconnect network on chips involves an increasing number of metal lines per interconnect level, more interconnect levels, and at the same time a reduction in the interconnect line critical dimensions.