This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.
Power Management Integrated Circuits and Technologies delivers a modern treatise on mixed-signal integrated circuit design for power management. Comprised of chapters authored by leading researchers from industry and academia, this definitive text: Describes circuit- and architectural-level innovations that meet advanced power and speed capabilities Explores hybrid inductive-capacitive converters for wide-range dynamic voltage scaling Presents innovative control techniques for single inductor dual output (SIDO) and single inductor multiple output (SIMO) converters Discusses cutting-edge design techniques including switching converters for analog/RF loads Compares the use of GaAs pHEMTs to CMOS devices for efficient high-frequency switching converters Thus, Power Management Integrated Circuits and Technologies provides comprehensive, state-of-the-art coverage of this exciting and emerging field of engineering.
Achieve enhanced performance with this guide to cutting-edge techniques for digitally-assisted analog and analog-assisted digital integrated circuit design. • Discover how architecture and circuit innovations can deliver improved performance in terms of speed, density, power, and cost • Learn about practical design considerations for high-performance scaled CMOS processes, FinFet devices and architectures, and the implications of FD SOI technology • Get up to speed with established circuit techniques that take advantage of scaled CMOS process technology in analog, digital, RF and SoC designs, including digitally-assisted techniques for data converters, DSP enabled frequency synthesizers, and digital controllers for switching power converters. With detailed descriptions, explanations, and practical advice from leading industry experts, this is an ideal resource for practicing engineers, researchers, and graduate students working in circuit design.
This book fills an information gap on cognitive radios, since the discussion focuses on the implementation issues that are unique to cognitive radios and how to solve them at both the architecture and circuit levels. This is the first book to describe in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement such systems. Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details. This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems.
This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors’ manuals, and program downloads
This book is based on the 18 tutorials presented during the 25th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of continuous-time sigma-delta modulators, automotive electronics, and power management. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.
Microsystems technologies have found their way into an impressive variety of applications, from mobile phones, computers, and displays to smart grids, electric cars, and space shuttles. This multidisciplinary field of research extends the current capabilities of standard integrated circuits in terms of materials and designs and complements them by creating innovative components and smaller systems that require lower power consumption and display better performance. Novel Advances in Microsystems Technologies and their Applications delves into the state of the art and the applications of microsystems and microelectronics-related technologies. Featuring contributions by academic and industrial researchers from around the world, this book: Examines organic and flexible electronics, from polymer solar cell to flexible interconnects for the co-integration of micro-electromechanical systems (MEMS) with complementary metal oxide semiconductors (CMOS) Discusses imaging and display technologies, including MEMS technology in reflective displays, the fabrication of thin-film transistors on glass substrates, and new techniques to display and quickly transmit high-quality images Explores sensor technologies for sensing electrical currents and temperature, monitoring structural health and critical industrial processes, and more Covers biomedical microsystems, including biosensors, point-of-care devices, neural stimulation and recording, and ultra-low-power biomedical systems Written for researchers, engineers, and graduate students in electrical and biomedical engineering, this book reviews groundbreaking technology, trends, and applications in microelectronics. Its coverage of the latest research serves as a source of inspiration for anyone interested in further developing microsystems technologies and creating new applications.
Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ?? DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced. Achieving a large bandwidth from ?? DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ?? DAC architectures, even in nanometer CMOS processes. Time-interleaved ?? (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs. The rst work is an 8-GS/s interleaved ?? DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ?? modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype. The performance of a two-channel interleaved ?? DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ?? DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented. The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ?? DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ?? DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.
This Handbook presents all aspects of memristor networks in an easy to read and tutorial style. Including many colour illustrations, it covers the foundations of memristor theory and applications, the technology of memristive devices, revised models of the Hodgkin-Huxley Equations and ion channels, neuromorphic architectures, and analyses of the dynamic behaviour of memristive networks. It also shows how to realise computing devices, non-von Neumann architectures and provides future building blocks for deep learning hardware. With contributions from leaders in computer science, mathematics, electronics, physics, material science and engineering, the book offers an indispensable source of information and an inspiring reference text for future generations of computer scientists, mathematicians, physicists, material scientists and engineers working in this dynamic field.
