This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.
Power Management Integrated Circuits and Technologies delivers a modern treatise on mixed-signal integrated circuit design for power management. Comprised of chapters authored by leading researchers from industry and academia, this definitive text: Describes circuit- and architectural-level innovations that meet advanced power and speed capabilities Explores hybrid inductive-capacitive converters for wide-range dynamic voltage scaling Presents innovative control techniques for single inductor dual output (SIDO) and single inductor multiple output (SIMO) converters Discusses cutting-edge design techniques including switching converters for analog/RF loads Compares the use of GaAs pHEMTs to CMOS devices for efficient high-frequency switching converters Thus, Power Management Integrated Circuits and Technologies provides comprehensive, state-of-the-art coverage of this exciting and emerging field of engineering.
This book explores near-threshold computing (NTC), a design-space using techniques to run digital chips (processors) near the lowest possible voltage. Readers will be enabled with specific techniques to design chips that are extremely robust; tolerating variability and resilient against errors. Variability-aware voltage and frequency allocation schemes will be presented that will provide performance guarantees, when moving toward near-threshold manycore chips. · Provides an introduction to near-threshold computing, enabling reader with a variety of tools to face the challenges of the power/utilization wall; · Demonstrates how to design efficient voltage regulation, so that each region of the chip can operate at the most efficient voltage and frequency point; · Investigates how performance guarantees can be ensured when moving towards NTC manycores through variability-aware voltage and frequency allocation schemes.
The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor’s geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides different techniques and architectures that allow for optimization.
This book covers algorithmic and hardware implementation techniques to enable embedded deep learning. The authors describe synergetic design approaches on the application-, algorithmic-, computer architecture-, and circuit-level that will help in achieving the goal of reducing the computational cost of deep learning algorithms. The impact of these techniques is displayed in four silicon prototypes for embedded deep learning. Gives a wide overview of a series of effective solutions for energy-efficient neural networks on battery constrained wearable devices; Discusses the optimization of neural networks for embedded deployment on all levels of the design hierarchy – applications, algorithms, hardware architectures, and circuits – supported by real silicon prototypes; Elaborates on how to design efficient Convolutional Neural Network processors, exploiting parallelism and data-reuse, sparse operations, and low-precision computations; Supports the introduced theory and design concepts by four real silicon prototypes. The physical realization’s implementation and achieved performances are discussed elaborately to illustrated and highlight the introduced cross-layer design concepts.
This Handbook presents all aspects of memristor networks in an easy to read and tutorial style. Including many colour illustrations, it covers the foundations of memristor theory and applications, the technology of memristive devices, revised models of the Hodgkin-Huxley Equations and ion channels, neuromorphic architectures, and analyses of the dynamic behaviour of memristive networks. It also shows how to realise computing devices, non-von Neumann architectures and provides future building blocks for deep learning hardware. With contributions from leaders in computer science, mathematics, electronics, physics, material science and engineering, the book offers an indispensable source of information and an inspiring reference text for future generations of computer scientists, mathematicians, physicists, material scientists and engineers working in this dynamic field.
Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ?? DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced. Achieving a large bandwidth from ?? DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ?? DAC architectures, even in nanometer CMOS processes. Time-interleaved ?? (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs. The rst work is an 8-GS/s interleaved ?? DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ?? modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype. The performance of a two-channel interleaved ?? DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ?? DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented. The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ?? DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ?? DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.
The increase of consumer, medical and sensors electronics using radio frequency (RF) and microwave (MW) circuits has implications on overall performances if design is not robust and optimized for a given applications. The current and later generation communication systems and Internet of Thing (IoT) demand for robust electronic circuits with optimized performance and functionality, but low cost, size, and power consumption. As a result, there is a need for a textbook that provides a comprehensive treatment of the subject. This book provides state-of-the-art coverage of RF and Microwave Techniques and Technologies, covers important topics: transmission-line theory, passive and semiconductor devices, active and passive microwave circuits and receiver systems, as well as antennas, noise and digital signal modulation schemes. With an emphasis on theory, design, and applications, this book is targeted to students, teachers, scientists, and practicing design engineers who are interested in broadening their knowledge of RF and microwave electronic circuit design. Readers will also benefit from a unique integration of theory and practice, provides the readers a solid understanding of the RF and microwave concepts, active and passive components, antenna, and modulation schemes. Readers will learn to solve common design problems ranging from selection of components, matching networks to biasing and stability, and digital modulation techniques. More importantly, it provides basic understanding in the analysis and design of RF and microwave circuits in a manner that is practiced in industry. This make sure that the know-how learned in this book can be effortlessly and straightway put into practice without any obstacles.
This Handbook serves as an authoritative reference book in the field of Neuroengineering. Neuroengineering is a very exciting field that is rapidly getting established as core subject matter for research and education. The Neuroengineering field has also produced an impressive array of industry products and clinical applications. It also serves as a reference book for graduate students, research scholars and teachers. Selected sections or a compendium of chapters may be used as “reference book” for a one or two semester graduate course in Biomedical Engineering. Some academicians will construct a “textbook” out of selected sections or chapters. The Handbook is also meant as a state-of-the-art volume for researchers. Due to its comprehensive coverage, researchers in one field covered by a certain section of the Handbook would find other sections valuable sources of cross-reference for information and fertilization of interdisciplinary ideas. Industry researchers as well as clinicians using neurotechnologies will find the Handbook a single source for foundation and state-of-the-art applications in the field of Neuroengineering. Regulatory agencies, entrepreneurs, investors and legal experts can use the Handbook as a reference for their professional work as well.
This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade. The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs). Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat. · Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem; · Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation; · Provides step-by-step solutions for detecting different types of counterfeit ICs; · Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC detection and avoidance, for industry and government.
