High-performance and hardware-aware computing
High-performance and hardware-aware computing

Author: Rainer Buchty

Publisher: KIT Scientific Publishing

Published: 2014-10-16

Total Pages: 70

ISBN-13: 3866446268

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High-performance system architectures are increasingly exploiting heterogeneity. The HipHaC workshop aims at combining new aspects of parallel, heterogeneous, and reconfigurable microprocessor technologies with concepts of high-performance computing and, particularly, numerical solution methods. Compute- and memory-intensive applications can only benefit from the fullhardware potential if all features on all levels are taken into account in a holistic approach.

Tools for High Performance Computing 2011
Tools for High Performance Computing 2011

Author: Holger Brunst

Publisher: Springer Science & Business Media

Published: 2012-09-21

Total Pages: 166

ISBN-13: 3642314767

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The proceedings of the 5th International Workshop on Parallel Tools for High Performance Computing provide an overview on supportive software tools and environments in the fields of System Management, Parallel Debugging and Performance Analysis. In the pursuit to maintain exponential growth for the performance of high performance computers the HPC community is currently targeting Exascale Systems. The initial planning for Exascale already started when the first Petaflop system was delivered. Many challenges need to be addressed to reach the necessary performance. Scalability, energy efficiency and fault-tolerance need to be increased by orders of magnitude. The goal can only be achieved when advanced hardware is combined with a suitable software stack. In fact, the importance of software is rapidly growing. As a result, many international projects focus on the necessary software.

Graphics Processing Unit-Based High Performance Computing in Radiation Therapy
Graphics Processing Unit-Based High Performance Computing in Radiation Therapy

Author: Xun Jia

Publisher: CRC Press

Published: 2018-09-21

Total Pages: 396

ISBN-13: 1482244799

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Use the GPU Successfully in Your Radiotherapy Practice With its high processing power, cost-effectiveness, and easy deployment, access, and maintenance, the graphics processing unit (GPU) has increasingly been used to tackle problems in the medical physics field, ranging from computed tomography reconstruction to Monte Carlo radiation transport simulation. Graphics Processing Unit-Based High Performance Computing in Radiation Therapy collects state-of-the-art research on GPU computing and its applications to medical physics problems in radiation therapy. Tackle Problems in Medical Imaging and Radiotherapy The book first offers an introduction to the GPU technology and its current applications in radiotherapy. Most of the remaining chapters discuss a specific application of a GPU in a key radiotherapy problem. These chapters summarize advances and present technical details and insightful discussions on the use of GPU in addressing the problems. The book also examines two real systems developed with GPU as a core component to accomplish important clinical tasks in modern radiotherapy. Translate Research Developments to Clinical Practice Written by a team of international experts in radiation oncology, biomedical imaging, computing, and physics, this book gets clinical and research physicists, graduate students, and other scientists up to date on the latest in GPU computing for radiotherapy. It encourages you to bring this novel technology to routine clinical radiotherapy practice.

High Performance Memory Systems
High Performance Memory Systems

Author: Haldun Hadimioglu

Publisher: Springer Science & Business Media

Published: 2011-06-27

Total Pages: 298

ISBN-13: 1441989870

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The State of Memory Technology Over the past decade there has been rapid growth in the speed of micropro cessors. CPU speeds are approximately doubling every eighteen months, while main memory speed doubles about every ten years. The International Tech nology Roadmap for Semiconductors (ITRS) study suggests that memory will remain on its current growth path. The ITRS short-and long-term targets indicate continued scaling improvements at about the current rate by 2016. This translates to bit densities increasing at two times every two years until the introduction of 8 gigabit dynamic random access memory (DRAM) chips, after which densities will increase four times every five years. A similar growth pattern is forecast for other high-density chip areas and high-performance logic (e.g., microprocessors and application specific inte grated circuits (ASICs)). In the future, molecular devices, 64 gigabit DRAMs and 28 GHz clock signals are targeted. Although densities continue to grow, we still do not see significant advances that will improve memory speed. These trends have created a problem that has been labeled the Memory Wall or Memory Gap.

Hardware-Aware Computation Reorganization for Memory Intensive Applications
Hardware-Aware Computation Reorganization for Memory Intensive Applications

Author: Orhan Kislal

Publisher:

Published: 2018

Total Pages:

ISBN-13:

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After hitting the power wall, the dramatic change in computer architecture from single core to multicore/manycore brings us new challenges on high performance computing, especially for data intensive applications. Data access costs dominate the execution times of most parallel applications and they are expected to be even more important in the future. Under these circumstances, the organization of data and computation across available resources becomes a major effect on the performance of the overall system. This dissertation explores the reorganization problem from a hardware-aware perspective to fully harness the underlying architecture and demonstrates various methods to improve the memory performance. These methods span both both domain-specific solutions for some memory-intensive kernels of high importance as well as domain-agnostic optimization techniques.This dissertation approaches the problem of reorganization from two different perspectives. While the traditional methods of organization for data and computation, namely mapping and scheduling, remain highly influential and beneficial; we also evaluate the idea of approximate computing in this context and reorganize data and computation based on their predicted importance. Our exploration includes following steps. On the domain-specific side; we apply mapping, scheduling and data layout reorganization techniques to the sparse matrix vector multiplication problem. In addition, we improve the k-means clustering algorithm with computation reordering as well as multiple skipping heuristics, and propose a cache skipping module for data mining algorithms and explore its benefits with recursive partitioning algorithms. On the domain-agnostic side; we explore location aware and data movement aware computation reorganization techniques, as well as, a code slicing technique that skips high-cost and low-importance data accesses. Our detailed experiments show significant improvements in all cases, up to 25% for domain-specific optimizations and up to 18% for domain-agnostic techniques.

Research Infrastructures for Hardware Accelerators
Research Infrastructures for Hardware Accelerators

Author: Yakun Sophia Shao

Publisher: Morgan & Claypool Publishers

Published: 2015-11-01

Total Pages: 101

ISBN-13: 162705832X

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Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas.

Power Aware Computing
Power Aware Computing

Author: Robert Graybill

Publisher: Springer Science & Business Media

Published: 2013-04-17

Total Pages: 387

ISBN-13: 1475762178

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With the advent of portable and autonomous computing systems, power con sumption has emerged as a focal point in many research projects, commercial systems and DoD platforms. One current research initiative, which drew much attention to this area, is the Power Aware Computing and Communications (PAC/C) program sponsored by DARPA. Many of the chapters in this book include results from work that have been supported by the PACIC program. The performance of computer systems has been tremendously improving while the size and weight of such systems has been constantly shrinking. The capacities of batteries relative to their sizes and weights has been also improv ing but at a rate which is much slower than the rate of improvement in computer performance and the rate of shrinking in computer sizes. The relation between the power consumption of a computer system and it performance and size is a complex one which is very much dependent on the specific system and the technology used to build that system. We do not need a complex argument, however, to be convinced that energy and power, which is the rate of energy consumption, are becoming critical components in computer systems in gen eral, and portable and autonomous systems, in particular. Most of the early research on power consumption in computer systems ad dressed the issue of minimizing power in a given platform, which usually translates into minimizing energy consumption, and thus, longer battery life.